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CY7C1357A
CY7C1355A
256K x 36/512K x 18 Synchronous Flow-Thru
SRAM with NoBL™ Architecture
Features
• Zero Bus Latency, no dead cycles between write and
read cycles
• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns
• Fast clock speed: 133, 117, and 100 MHz
• Fast OE access time: 6.5, 7.0, and 7.5ns
• Internally synchronized registered outputs eliminate
the need to control OE
• 3.3V –5% and +5% power supply
• 3.3V or 2.5V I/O supply
• Single WEN (READ/WRITE) control pin
• Positive clock-edge triggered, address, data, and
control signal registers for fully pipelined applications
• Interleaved or linear four-word burst capability
• Individual byte write (BWa–BWd) control (may be tied
LOW)
• CEN pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
• Automatic Power-down feature available using ZZ
mode or CE deselect.
• JTAG boundary scan (except CY7C1357A)
• Low-profile 119-bump, 14-mm × 22-mm BGA (Ball Grid
Array) for CY7C1355A, and 100-pin TQFP packages for
both devices
Functional Description
The CY7C1355A and CY7C1357A SRAMs are designed to
eliminate dead cycles when transitions from READ to WRITE
or vice versa. These SRAMs are optimized for 100 percent bus
utilization and achieves Zero Bus Latency (ZBL). They
integrate 262,144 × 36 and 524,288 × 18 SRAM cells, respec-
tively, with advanced synchronous peripheral circuitry and a
2-bit counter for internal burst operation. These employ
high-speed, low power CMOS designs using advanced
triple-layer polysilicon, double-layer metal technology. Each
memory cell consists of Six transistors.
Selection Guide
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, depth-expansion
Chip Enables (CE, CE2, and CE3), Cycle Start Input (ADV/LD),
Clock Enable (CEN), Byte Write Enables (BWa, BWb, BWc,
and BWd), and read-write control (WEN). BWc and BWd apply
to CY7C1355A only.
Address and control signals are applied to the SRAM during
one clock cycle, and one cycle later, its associated data
occurs, either read or write.
A Clock Enable (CEN) pin allows operation of the
CY7C1355A/CY7C1357A to be suspended as long as
necessary. All synchronous inputs are ignored when (CEN) is
HIGH and the internal device registers will hold their previous
values.
There are three Chip Enable pins (CE, CE2, CE3) that allow
the user to deselect the device when desired. If any one of
these three are not active when ADV/LD is LOW, no new
memory operation can be initiated and any burst cycle in
progress is stopped. However, any pending data transfers
(read or write) will be completed. The data bus will be in
high-impedance state one cycle after chip is deselected or a
write cycle is initiated.
The CY7C1355A and CY7C1357A have an on-chip 2-bit burst
counter. In the burst mode, the CY7C1355A and CY7C1357A
provide four cycles of data for a single address presented to
the SRAM. The order of the burst sequence is defined by the
MODE input pin. The MODE pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load
a new external address (ADV/LD = LOW) or increment the
internal burst counter (ADV/LD = HIGH)
Output Enable (OE), Sleep Enable (ZZ) and burst sequence
select (MODE) are the asynchronous signals. OE can be used
to disable the outputs at any given time. ZZ may be tied to
LOW if it is not used.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
7C1355A-133
7C1357A-133
6.5
410
30
7C1355A-117
7C1357A-117
7
385
30
7C1355A-100
7C1357A-100
7.5
350
30
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05265 Rev. *A
Revised August 23, 2002
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