CY7C1357A Overview
CY7C1357A CY7C1355A 256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL™ Architecture.
CY7C1357A Key Features
- Zero Bus Latency, no dead cycles between write and read cycles
- Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns
- Fast clock speed: 133, 117, and 100 MHz
- Fast OE access time: 6.5, 7.0, and 7.5ns
- Internally synchronized registered outputs eliminate the need to control OE
- 3.3V -5% and +5% power supply 3.3V or 2.5V I/O supply Single WEN (READ/WRITE) control pin Positive clock-edge triggered,