CY7C1347B Overview
The CY7C1347B is a 3.3V, 128K by 36 synchronous-pipelined cache SRAM designed to support zero-wait-state secondary cache with minimal glue logic.
CY7C1347B Key Features
- Supports 100-MHz bus for Pentium and PowerPC™ operations with zero wait states
- Fully registered inputs and outputs for pipelined operation
- 128K by 36 mon I/O architecture
- 3.3V core power supply
- 2.5V/3.3V I/O operation
- Fast clock-to-output times
- 3.5 ns (for 166-MHz device)
- 4.0 ns (for 133-MHz device)