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Cypress Semiconductor Electronic Components Datasheet

CY7C1345G Datasheet

4-Mbit Flow-Through Sync SRAM

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CY7C1345G
4-Mbit (128K × 36) Flow-Through Sync SRAM
4-Mbit (128K × 36) Flow-Through Sync SRAM
Features
128K × 36 common I/O
3.3 V core power supply (VDD)
2.5 V or 3.3 V I/O supply (VDDQ)
Fast clock-to-output times
8.0 ns (100 MHz version)
Provide high performance 2-1-1-1 access rate
User selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self timed write
Asynchronous output enable
Available in Pb-free 100-pin TQFP package
ZZ sleep mode option
Functional Description
The CY7C1345G is a 128K × 36 synchronous cache RAM
designed to interface with high speed microprocessors with
minimum glue logic. The maximum access delay from clock rise
is 8.0 ns (100 MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are gated
by registers controlled by a positive edge triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address pipelining chip enable (CE1), depth expansion
chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP,
and ADV), write enables (BWx, and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
The CY7C1345G enables either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses are initiated with the processor
address strobe (ADSP) or the cache controller address strobe
(ADSC) inputs.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) is active. Subsequent burst addresses
are internally generated as controlled by the Advance pin (ADV).
The CY7C1345G operates from a +3.3 V core power supply
while all outputs operate with either a +2.5 or +3.3 V supply. All
inputs and outputs are JEDEC standard JESD8-5 compatible.
For a complete list of related documentation, click here.
Selection Guide
Maximum access time
Maximum operating current
Maximum standby current
Description
100 MHz
8.0
205
40
Unit
ns
mA
mA
Errata: For information on silicon errata, see Errata on page 22. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05517 Rev. *P
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 7, 2016


Cypress Semiconductor Electronic Components Datasheet

CY7C1345G Datasheet

4-Mbit Flow-Through Sync SRAM

No Preview Available !

Logic Block Diagram
A 0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW D
BW C
BW B
BW A
BWE
GW
CE1
CE2
CE3
OE
ZZ
ADDRESS
REGISTER
A [1:0]
BURST Q1
COUNTER
AND LOGIC
CLR Q0
DQ D, DQP D
BYTE
WRITE REGISTER
DQ C, DQP C
BYTE
WRITE REGISTER
DQ B, DQP B
BYTE
WRITE REGISTER
DQ A, DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
SLEEP
CONTROL
CY7C1345G
DQ D, DQP D
BYTE
WRITE REGISTER
DQ C, DQP C
BYTE
WRITE REGISTER
DQ B, DQP B
BYTE
WRITE REGISTER
DQ A, DQP A
BYTE
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQ s
DQP A
DQP B
DQP C
DQP D
INPUT
REGISTERS
Document Number: 38-05517 Rev. *P
Page 2 of 25


Part Number CY7C1345G
Description 4-Mbit Flow-Through Sync SRAM
Maker Cypress Semiconductor
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CY7C1345G Datasheet PDF






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