CY7C13451G
4-Mbit (128K × 36) Flow-Through
Sync SRAM
4-Mbit (128K × 36) Flow-Through Sync SRAM
Features
■ 128K × 36 common I/O
■ 3.3 V core Power Supply (VDD)
■ 2.5 V or 3.3 V I/O Supply (VDDQ)
■ Fast Clock-to-output times
❐ 8.0 ns (100 MHz version)
■ Provide high performance 2-1-1-1 access rate
■ User selectable burst counter supporting Intel Pentium
interleaved or Linear Burst Sequences
■ Separate Processor and Controller Address Strobes
■ Synchronous Self Timed Write
■ Asynchronous output enable
■ Available in Pb-free 165-ball FBGA Package
■ ZZ Sleep Mode option
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Description
Functional Description
The CY7C13451G is a 128K × 36 synchronous cache RAM
designed to interface with high speed microprocessors with
minimum glue logic. The maximum access delay from clock rise
is 8.0 ns (100 MHz version). A 2 bit on-chip counter captures the
first address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are gated
by registers controlled by a positive edge triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address pipelining Chip Enable (CE1), depth expansion
Chip Enables (CE2 and CE3), Burst Control inputs (ADSC,
ADSP, and ADV), Write Enables (BWx, and BWE), and Global
Write (GW). Asynchronous inputs include the Output Enable
(OE) and the ZZ pin.
The CY7C13451G enables either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses are initiated with the Processor
Address Strobe (ADSP) or the cache Controller Address Strobe
(ADSC) inputs.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) is active. Subsequent burst addresses
are internally generated as controlled by the Advance pin (ADV).
The CY7C13451G operates from a +3.3 V core power supply
while all outputs operate with either a +2.5 or +3.3 V supply. All
inputs and outputs are JEDEC standard JESD8-5 compatible.
For a complete list of related documentation, click here.
100 MHz
8.0
180
60
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-88572 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 29, 2016
