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CY7C1316CV18 Datasheet

(CY7C1xxxCV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture

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CY7C1316CV18, CY7C1916CV18
CY7C1318CV18, CY7C1320CV18
18-Mbit DDR-II SRAM 2-Word
Burst Architecture
Features
Functional Description
18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)
267 MHz clock for high bandwidth
2-word burst for reducing address bus frequency
Double Data Rate (DDR) interfaces
www.DataShee(td4aUt.acotrmansferred at 534 MHz) at 267 MHz
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
Synchronous internally self-timed writes
DDR-II operates with 1.5 cycle read latency when the DLL is
enabled
Operates similar to a DDR-I device with 1 cycle read latency in
DLL off mode
1.8V core power supply with HSTL inputs and outputs
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4V–VDD)
Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 compatible test access port
Delay Lock Loop (DLL) for accurate data placement
The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and
CY7C1320CV18 are 1.8V Synchronous Pipelined SRAMs
equipped with DDR-II architecture. The DDR-II consists of an
SRAM core with advanced synchronous peripheral circuitry and
a one-bit burst counter. Addresses for read and write are latched
on alternate rising edges of the input (K) clock. Write data is
registered on the rising edges of both K and K. Read data is
driven on the rising edges of C and C if provided, or on the rising
edge of K and K if C/C are not provided. Each address location
is associated with two 8-bit words in the case of CY7C1316CV18
and two 9-bit words in the case of CY7C1916CV18 that burst
sequentially into or out of the device. The burst counter always
starts with a ‘0’ internally in the case of CY7C1316CV18 and
CY7C1916CV18. For CY7C1318CV18 and CY7C1320CV18,
the burst counter takes in the least significant bit of the external
address and bursts two 18-bit words (in the case of
CY7C1318CV18) of two 36-bit words (in the case of
CY7C1320CV18) sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs, D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need to capture data
separately from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Configurations
CY7C1316CV18 – 2M x 8
CY7C1916CV18 – 2M x 9
CY7C1318CV18 – 1M x 18
CY7C1320CV18 – 512K x 36
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
267 MHz
267
x8 775
x9 780
x18 805
x36 855
250 MHz
250
705
710
730
775
200 MHz
200
575
580
600
635
167 MHz
167
490
490
510
540
Unit
MHz
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-07160 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 26, 2007
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Cypress Semiconductor Electronic Components Datasheet

CY7C1316CV18 Datasheet

(CY7C1xxxCV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture

No Preview Available !

Logic Block Diagram (CY7C1316CV18)
CY7C1316CV18, CY7C1916CV18
CY7C1318CV18, CY7C1320CV18
A(19:0)
20
LD
www.DataSheet4U.com
K
K
DOFF
Address
Register
CLK
Gen.
VREF
R/W
NWS[1:0]
Control
Logic
Write
Reg
Write
Reg
8
Read Data Reg.
16
8
8
Output
Logic
Control
R/W
C
C
Reg.
Reg.
Reg. 8
8
8
CQ
CQ
DQ[7:0]
Logic Block Diagram (CY7C1916CV18)
A(19:0)
20
LD
K
K
DOFF
VREF
R/W
BWS[0]
Address
Register
CLK
Gen.
Control
Logic
Write
Reg
Write
Reg
9
Read Data Reg.
18
9
9
Output
Logic
Control
R/W
C
C
Reg.
Reg.
Reg. 9
9
9
CQ
CQ
DQ[8:0]
Document Number: 001-07160 Rev. *C
Page 2 of 29
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Part Number CY7C1316CV18
Description (CY7C1xxxCV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
Maker Cypress Semiconductor
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