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CY7C1315AV18 Datasheet (CY7C131xAV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture

Manufacturer: Cypress (now Infineon)

Overview: PRELIMINARY CY7C1311AV18 CY7C1313AV18 CY7C1315AV18 18-Mb QDR™-II SRAM 4-Word Burst.

Download the CY7C1315AV18 datasheet PDF. This datasheet also includes the CY7C1311AV18 variant, as both parts are published together in a single manufacturer document.

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General Description

The CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture.

QDR-II architecture consists of two separate ports to access the memory array.

The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations.

Key Features

  • Separate Independent Read and Write Data Ports.
  • Supports concurrent transactions.
  • 250-MHz Clock for High Bandwidth.
  • 4-Word Burst for reducing address bus frequency.
  • Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred at 500 MHz) at 250 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two output clocks (C and C) accounts for clock skew and flight time mismatchi.

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C1315BV18 (CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1315CV18 (CY7C1x1xCV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1315JV18 (CY7C1x1xJV18) 18-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1315KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C131 1K x 8 Dual-Port Static RAM
CY7C1310BV18 1.8V Synchronous Pipelined SRAM
CY7C1311AV18 (CY7C131xAV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1311BV18 (CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1311CV18 (CY7C1x1xCV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
CY7C1311JV18 (CY7C1x1xJV18) 18-Mbit QDR II SRAM 4-Word Burst Architecture