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CY7C1306BV18 - 18-Mbit Burst of 2 Pipelined SRAM

Download the CY7C1306BV18 datasheet PDF. This datasheet also covers the CY7C1303BV18 variant, as both devices belong to the same 18-mbit burst of 2 pipelined sram family and are provided as variant models within a single manufacturer datasheet.

General Description

Separate independent Read and Write data ports Supports concurrent transactions 167-MHz Clock for high bandwidth 2.5 ns Clock-to-Valid access time 2-Word Burst on all accesses Double Data Rate (DDR) interfaces on both Read and Write Ports

Key Features

  • Functional.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1303BV18-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C130 1K x 8 Dual-Port Static RAM
CY7C1302CV25 9-Mbit Burst of Two Pipelined SRAMs
CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs
CY7C1303BV18 18-Mbit Burst of 2 Pipelined SRAM
CY7C1303BV25 18-Mbit Burst of Two-Pipelined SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CY7C1303BV18 CY7C1306BV18 18-Mbit Burst of 2 Pipelined SRAM with QDR™ Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz Clock for high bandwidth — 2.5 ns Clock-to-Valid access time • 2-Word Burst on all accesses • Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred at 333 MHz) @167 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches. • Single multiplexed address input bus latches address inputs for both Read and Write ports • Separate Port Selects for depth expansion • Synchronous internally self-timed writes • 1.