CY7C1306BV18 sram equivalent, 18-mbit burst of 2 pipelined sram.
Functional Description
* Separate independent Read and Write data ports — Supports concurrent transactions
* 167-MHz Clock for high bandwidth — 2.5 ns Clock-to-.
* Separate independent Read and Write data ports — Supports concurrent transactions
* 167-MHz Clock for high bandwidth — 2.5 ns Clock-to-Valid access time
* 2-Word Burst on all accesses
* Double Data Rate (DDR) interfaces on both Rea.
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