CY7C1305BV18 Description
Separate independent Read and Write data ports Supports concurrent transactions 167-MHz Clock for high bandwidth 2.5 ns Clock-to-Valid access time 4-Word Burst for reducing the address bus frequency Double Data Rate (DDR) interfaces on both Read & Write Ports (data transferred at 333 MHz) @167 MHz Two input clocks (K and K) for precise DDR timing SRAM uses rising edges only Two input clocks for output data (C and C)...
CY7C1305BV18 Key Features
- Separate independent Read and Write data ports
- Supports concurrent transactions
- 167-MHz Clock for high bandwidth
- 2.5 ns Clock-to-Valid access time
- 4-Word Burst for reducing the address bus frequency
- Double Data Rate (DDR) interfaces on both Read & Write
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Two input clocks for output data (C and C) to minimize
- Single multiplexed address input bus latches address