Functional Description
* Separate independent Read and Write data ports — Supports concurrent transactions
* 167-MHz Clock for high bandwidth — 2.5 ns Clock-to-.

* Separate independent Read and Write data ports — Supports concurrent transactions
* 167-MHz Clock for high bandwidth — 2.5 ns Clock-to-Valid access time
* 4-Word Burst for reducing the address bus frequency
* Double Data Rate (DDR).

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