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Cypress Semiconductor Electronic Components Datasheet

CY7C1303BV25 Datasheet

18-Mbit Burst of Two-Pipelined SRAM

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CY7C1303BV25
18-Mbit Burst of Two-Pipelined SRAM
with QDR® Architecture
18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture
Features
Separate independent read and write data ports
Supports concurrent transactions
167 MHz clock for high bandwidth
2.5 ns clock-to-valid access time
Two word burst on all accesses
Double data rate (DDR) interfaces on both read and write ports
(data transferred at 333 MHz) at 167 MHz
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches.
Single multiplexed address input bus latches address inputs
for both read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
2.5 V core power supply with HSTL inputs and outputs
Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4 V to 1.9 V)
JTAG Interface
Variable Impedance HSTL
Configurations
CY7C1303BV25 – 1M × 18
Functional Description
The CY7C1303BV25 is 2.5 V synchronous pipelined SRAM
equipped with QDR® architecture. QDR architecture consists of
two separate ports to access the memory array. The read port
has dedicated data outputs to support read operations and the
write port has dedicated data inputs to support write operations.
Access to each port is accomplished through a common address
bus. The Read address is latched on the rising edge of the K
clock and the Write address is latched on the rising edge of K
clock. QDR has separate data inputs and data outputs to
completely eliminate the need to “turn around” the data bus
required with common I/O devices. Accesses to the
CY7C1303BV25 Read and Write ports are completely
independent of one another. All accesses are initiated
synchronously on the rising edge of the positive input clock (K).
In order to maximize data throughput, both Read and Write ports
are equipped with Double Data Rate (DDR) interfaces.
Therefore, data can be transferred into the device on every rising
edge of both input clocks (K and K) and out of the device on every
rising edge of the output clock (C and C, or K and K when in
single clock mode) thereby maximizing performance while
simplifying system design. Each address location is associated
with two 18-bit words (CY7C1303BV25) that burst sequentially
into or out of the device.
Depth expansion is accomplished with a port select input for
each port. Each Port Selects allow each port to operate
independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Maximum operating frequency
Maximum operating current
Description
CY7C1303BV25-167
167
500
Unit
MHz
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05627 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 26, 2016


Cypress Semiconductor Electronic Components Datasheet

CY7C1303BV25 Datasheet

18-Mbit Burst of Two-Pipelined SRAM

No Preview Available !

CY7C1303BV25
Logic Block Diagram – CY7C1303BV25
D[17:0]
18
A(18:0)
19
K
K
Address
Register
CLK
Gen.
VREF
WPS
BWS0
BWS1
Control
Logic
Write
Data Reg
Write
Data Reg
512 K × 18 512 K × 18
Memory Memory
Array
Array
Read Data Reg.
36 18
18
Address
Register
19 A(18:0)
Control
Logic
RPS
C
C
Reg.
Reg.
Reg. 18
18
18
Q[17:0]
Document Number: 38-05627 Rev. *I
Page 2 of 26


Part Number CY7C1303BV25
Description 18-Mbit Burst of Two-Pipelined SRAM
Maker Cypress Semiconductor
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