Datasheet4U Logo Datasheet4U.com

CY7C1303BV25 Datasheet 18-Mbit Burst of Two-Pipelined SRAM

Manufacturer: Cypress (now Infineon)

📥 Download Datasheet

Overview

CY7C1303BV25 18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture 18-Mbit Burst of Two-Pipelined SRAM with QDR®.

Key Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 167 MHz clock for high bandwidth.
  • 2.5 ns clock-to-valid access time.
  • Two word burst on all accesses.
  • Double data rate (DDR) interfaces on both read and write ports (data transferred at 333 MHz) at 167 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mism.

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C1303BV18 18-Mbit Burst of 2 Pipelined SRAM
CY7C130 1K x 8 Dual-Port Static RAM
CY7C1302CV25 9-Mbit Burst of Two Pipelined SRAMs
CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs
CY7C1304DV25 9-Mbit Burst of 4 Pipelined SRAM
CY7C1305BV18 18-Mbit Burst of 4 Pipelined SRAM
CY7C1305BV25 18-Mbit Burst of 4 Pipelined SRAM
CY7C1306BV18 18-Mbit Burst of 2 Pipelined SRAM
CY7C1307BV18 18-Mbit Burst of 4 Pipelined SRAM
CY7C1307BV25 18-Mbit Burst of 4 Pipelined SRAM