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CY7C1298H Datasheet 1-Mbit (64K x 18) Pipelined DCD Sync SRAM

Manufacturer: Cypress (now Infineon)

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General Description

[1] The CY7C1298H SRAM integrates 64K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation.

All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).

The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:B], and BWE), and Global Write (GW).

Overview

www.DataSheet4U.com CY7C1298H 1-Mbit (64K x 18) Pipelined DCD Sync.

Key Features

  • Registered inputs and outputs for pipelined operation.
  • Optimal for performance (Double-Cycle deselect).
  • Depth expansion without wait state.
  • 64K × 18-bit common I/O architecture.
  • 3.3V core power supply (VDD).
  • 2.5V/3.3V I/O power supply (VDDQ).
  • Fast clock-to-output times.
  • 3.5 ns (for 166-MHz device).
  • Provide high-performance 3-1-1-1 access rate.
  • User-selectable burst counter supporting Intel® Pentium® interl.

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C1298F 1-Mbit (64K x 18) Pipelined DCD Sync SRAM
CY7C1292DV18 (CY7C1292DV18 / CY7C1294DV18) SRAM 2-Word Burst Architecture
CY7C1294DV18 (CY7C1292DV18 / CY7C1294DV18) SRAM 2-Word Burst Architecture
CY7C1297F 1-Mbit (64K x 18) Flow-Through Sync SRAM
CY7C1212F 1-Mbit (64K x 18) Pipelined Sync SRAM
CY7C1212H 1-Mbit (64K x 18) Pipelined Sync SRAM
CY7C1214F 1-Mb (32K x 32) Flow-Through Sync SRAM
CY7C1214H 1-Mbit (32K x 32) Flow-Through Sync SRAM
CY7C1215F 1-Mb (32K x 32) Pipelined Sync SRAM
CY7C1215H 1-Mbit (32K x 32) Pipelined Sync SRAM