CY7C1298H - 1-Mbit (64K x 18) Pipelined DCD Sync SRAM

Product Overview

Cypress Semiconductor

Datasheet Details

Part number	CY7C1298H
Manufacturer	Cypress Semiconductor
File Size	407.12 KB
Description	1-Mbit (64K x 18) Pipelined DCD Sync SRAM
Datasheet	CY7C1298H Datasheet
Additional preview pages of the CY7C1298H datasheet.

Product details

Description

1] The CY7C1298H SRAM integrates 64K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation.All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:B], and BWE), and Global Write (GW

Features

Registered inputs and outputs for pipelined operation.
Optimal for performance (Double-Cycle deselect).
Depth expansion without wait state.
64K × 18-bit common I/O architecture.
3.3V core power supply (VDD).
2.5V/3.3V I/O power supply (VDDQ).
Fast clock-to-output times.
3.5 ns (for 166-MHz device).
Provide high-performance 3-1-1-1 access rate.
User-selectable burst counter supporting Intel® Pentium® interl.

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Other Datasheets by Cypress Semiconductor

CY7C1298F - 1-Mbit (64K x 18) Pipelined DCD Sync SRAM
CY7C1292DV18 - (CY7C1292DV18 / CY7C1294DV18) SRAM 2-Word Burst Architecture
CY7C1294DV18 - (CY7C1292DV18 / CY7C1294DV18) SRAM 2-Word Burst Architecture
CY7C1297F - 1-Mbit (64K x 18) Flow-Through Sync SRAM
CY7C1212F - 1-Mbit (64K x 18) Pipelined Sync SRAM
CY7C1212H - 1-Mbit (64K x 18) Pipelined Sync SRAM

Published: Oct 4, 2007 |