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Cypress Semiconductor Electronic Components Datasheet

CY7C1298F Datasheet

1-Mbit (64K x 18) Pipelined DCD Sync SRAM

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CY7C1298F
1-Mbit (64K x 18) Pipelined DCD Sync SRAM
Features
Functional Description[1]
• Registered inputs and outputs for pipelined operation
• Optimal for performance (Double-Cycle deselect)
— Depth expansion without wait state
• 64K × 18-bit common I/O architecture
• 3.3V –5% and +10% core power supply (VDD)
• 3.3V I/O supply (VDDQ)
• Fast clock-to-output times
— 3.5ns (for 166-MHz device)
— 4.0ns (for 133-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
Pentiuminterleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous Output Enable
• JEDEC-standard 100-pin TQFP package and pinout
• “ZZ” Sleep Mode option
The CY7C1298F SRAM integrates 65,536x18 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CCoEn1tr)o, ldeinppthu-tesxp(AanDsSioCn,
Chip Enables
ADSP, and
(CE2
ADV),
aWndriCteE3E),naBbulresst
i(nBpWut[sA:Bin],claundde
BWE), and Global
the Output Enable
Write (GW).
(OE) and the
Asynchronous
ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two bytes wide as
controlled by the byte write control inputs. GW active LOW
causes all bytes to be written. This device incorporates an
additional pipelined enable register which delays turning off
the output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penal-
izing system performance.
The CY7C1298F operates from a +3.3V core power supply
while all outputs operate with a +3.3V supply. All inputs and
outputs are JEDEC-standard JESD8-5-compatible.
Selection Guide
166 MHz 133 MHz
Maximum Access Time
3.5 4.0
Maximum Operating Current
240 225
Maximum CMOS Standby Current
40 40
Shaded areas contain advance information. Please contact your local CYpress sales representative for availability of these parts.
Note:
1. . For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05417 Rev. *A
Revised April 7, 2004


Cypress Semiconductor Electronic Components Datasheet

CY7C1298F Datasheet

1-Mbit (64K x 18) Pipelined DCD Sync SRAM

No Preview Available !

Functional Block Diagram—64Kx18
A0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ADDRESS
REGISTER
2 A[1:0]
Q1
BURST
COUNTER AND
LOGIC
CLR Q0
DQB, DQPB
BYTE
WRITE REGISTER
DQA , DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
ZZ SLEEP
CONTROL
CY7C1298F
DQB , DQPB
BYTE
WRITE DRIVER
DQA, DQPA
BYTE
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs,
DQPA
DQPB
INPUT
REGISTERS
Document #: 38-05417 Rev. *A
Page 2 of 15


Part Number CY7C1298F
Description 1-Mbit (64K x 18) Pipelined DCD Sync SRAM
Maker Cypress Semiconductor
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CY7C1298F Datasheet PDF






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