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Cypress Semiconductor Electronic Components Datasheet

CY7C1297F Datasheet

1-Mbit (64K x 18) Flow-Through Sync SRAM

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CY7C1297F
1-Mbit (64K x 18) Flow-Through Sync SRAM
Features
• 64K x 18 common I/O
• 3.3V –5% and +10% core power supply (VDD)
• 3.3V I/O supply (VDDQ)
• Fast clock-to-output times
— 6.5 ns (133-MHz version)
— 7.5 ns (117-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel
Pentiuminterleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Supports 3.3V I/O level
• Offered in JEDEC-standard 100-pin TQFP
• “ZZ” Sleep Mode option
Functional Description[1]
The CY7C1297F is a 131,072 x 18 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
Logic Block Diagram
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE1), depth-expansion Chip Enables (CE2 and CE3), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW[A:B], and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
The CY7C1297F allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs. Address advancement is
controlled by the Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1297F operates from a +3.3V core power supply
while all outputs may operate with either a +3.3V supply. All
inputs and outputs are JEDEC-standard JESD8-5-compatible.
A0,A1,A
MODE
ADV
CLK
ADSC
ADSP
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ADDRESS
REGISTER
A[1:0]
BURST Q1
COUNTER AND
LOGIC
CLR Q0
DQB,DQPB
WRITE REGISTER
DQA,DQPA
WRITE REGISTER
ENABLE
REGISTER
DQB,DQPB
WRITE DRIVER
DQA,DQPA
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQs
DQPA
DQPB
INPUT
REGISTERS
ZZ SLEEP
CONTROL
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05429 Rev. *B
Revised December 21, 2004


Cypress Semiconductor Electronic Components Datasheet

CY7C1297F Datasheet

1-Mbit (64K x 18) Flow-Through Sync SRAM

No Preview Available !

Selection Guide
133 MHz
117 MHz
Maximum Access Time
6.5 7.5
Maximum Operating Current
225 220
Maximum Standby Current
40 40
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of this part.
Pin Configuration
100-Pin TQFP
CY7C1297F
Unit
ns
mA
mA
BYTE B
NC
NC
NC
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1297F
80 A
79 NC
78 NC
77 VDDQ
76 VSS
75 NC
74 DQPA
73 DQA
72 DQA
71 VSS
70 VDDQ
69 DQA
68 DQA
67 VSS
66 NC
65 VDD
64 ZZ
63 DQA
62 DQA
61 VDDQ
60 VSS
59 DQA
58 DQA
57 NC
56 NC
55 VSS
54 VDDQ
53 NC
52 NC
51 NC
BYTE A
Document #: 38-05429 Rev. *B
Page 2 of 15


Part Number CY7C1297F
Description 1-Mbit (64K x 18) Flow-Through Sync SRAM
Maker Cypress Semiconductor
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CY7C1297F Datasheet PDF






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