CY7C12701KV18 Datasheet Cypress Semiconductor

Features and Benefits

■ 36-Mbit density (4 M × 8, 4 M × 9, 2 M × 18, 1 M × 36)
■ 550 MHz clock for high bandwidth
■ 2-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
■ Available in 2.5 clock cycle latency
■ Two input clocks (K and K) for precise .