CY7C12701KV18 Overview
CY7C12661KV18, CY7C12771KV18 CY7C12681KV18, CY7C12701KV18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read.
CY7C12701KV18 Key Features
- 550 MHz clock for high bandwidth
- 2-word burst for reducing address bus frequency
- Double data rate (DDR) interfaces
- Available in 2.5 clock cycle latency
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Echo clocks (CQ and CQ) simplify data capture in high speed
- Data valid pin (QVLD) to indicate valid data on the output
- Synchronous internally self-timed writes
- DDR II+ operates with 2.5 cycle read latency when DOFF is