CY7C1268KV18
Key Features
- 550 MHz clock for high bandwidth
- Two-word burst for reducing address bus frequency
- Double data rate (DDR) interfaces (data transferred at
- Available in 2.5 clock cycle latency
- Two input clocks (K and K) for precise DDR timing
- Echo clocks (CQ and CQ) simplify data capture in high speed
- Data valid pin (QVLD) to indicate valid data on the output
- Synchronous internally self-timed writes
- DDR II+ operates with 2.5 cycle read latency when DOFF is
- Operates similar to DDR I device with 1 cycle read latency when
