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CY7C12681KV18 Datasheet 1.8 V synchronous pipelined SRAM

Manufacturer: Cypress (now Infineon)

Download the CY7C12681KV18 datasheet PDF. This datasheet also includes the CY7C12661KV18 variant, as both parts are published together in a single manufacturer document.

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Note: The manufacturer provides a single datasheet file (CY7C12661KV18-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

Overview

CY7C12661KV18, CY7C12771KV18 CY7C12681KV18, CY7C12701KV18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.

Key Features

  • 36-Mbit density (4 M × 8, 4 M × 9, 2 M × 18, 1 M × 36).
  • 550 MHz clock for high bandwidth.
  • 2-word burst for reducing address bus frequency.
  • Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz.
  • Available in 2.5 clock cycle latency.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Echo clocks (CQ and CQ) simplify data capture in high speed systems.
  • Data valid pin (QVLD) to indicate valid data on the.

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C1268KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C1261V18 1.8V Synchronous Pipelined SRAM
CY7C1262XV18 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
CY7C1263KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C1263V18 1.8V Synchronous Pipelined SRAM
CY7C1263XV18 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
CY7C1264XV18 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
CY7C1265KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C1265V18 1.8V Synchronous Pipelined SRAM
CY7C1265XV18 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture