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CY7C12681KV18 - 1.8 V synchronous pipelined SRAM

This page provides the datasheet information for the CY7C12681KV18, a member of the CY7C12661KV18 1.8 V synchronous pipelined SRAM family.

Datasheet Summary

Features

  • 36-Mbit density (4 M × 8, 4 M × 9, 2 M × 18, 1 M × 36).
  • 550 MHz clock for high bandwidth.
  • 2-word burst for reducing address bus frequency.
  • Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz.
  • Available in 2.5 clock cycle latency.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Echo clocks (CQ and CQ) simplify data capture in high speed systems.
  • Data valid pin (QVLD) to indicate valid data on the.

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Datasheet preview – CY7C12681KV18

Datasheet Details

Part number CY7C12681KV18
Manufacturer Cypress Semiconductor
File Size 571.92 KB
Description 1.8 V synchronous pipelined SRAM
Datasheet download datasheet CY7C12681KV18 Datasheet
Additional preview pages of the CY7C12681KV18 datasheet.

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Full PDF Text Transcription

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CY7C12661KV18, CY7C12771KV18 CY7C12681KV18, CY7C12701KV18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features ■ 36-Mbit density (4 M × 8, 4 M × 9, 2 M × 18, 1 M × 36) ■ 550 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz ■ Available in 2.5 clock cycle latency ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Echo clocks (CQ and CQ) simplify data capture in high speed systems ■ Data valid pin (QVLD) to indicate valid data on the output ■ Synchronous internally self-timed writes ■ DDR II+ operates with 2.
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