CY7C1265KV18 Overview
CY7C1263KV18/CY7C1265KV18 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency).
CY7C1265KV18 Key Features
- Separate independent read and write data ports
- Supports concurrent transactions
- 550 MHz clock for high bandwidth
- Four-word burst for reducing address bus frequency
- Double data rate (DDR) Interfaces on both read and write ports
- Available in 2.5 clock cycle latency
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Echo clocks (CQ and CQ) simplify data capture in high speed
- Data valid pin (QVLD) to indicate valid data on the output