CY7C1265KV18
Key Features
- Separate independent read and write data ports ❐ Supports concurrent transactions
- 550 MHz clock for high bandwidth
- Four-word burst for reducing address bus frequency
- Double data rate (DDR) Interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz
- Available in 2.5 clock cycle latency
- Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only
- Echo clocks (CQ and CQ) simplify data capture in high speed systems
- Data valid pin (QVLD) to indicate valid data on the output
- Single multiplexed address input bus latches address inputs for read and write ports
- Separate port selects for depth expansion
