CY7C1250KV18
Overview
- 36-Mbit density (2M × 18, 1M × 36)
- 450 MHz clock for high bandwidth
- Two-word burst for reducing address bus frequency
- Double data rate (DDR) interfaces (data transferred at 900 MHz) at 450 MHz
- Available in 2.0 clock cycle latency
- Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only
- Echo clocks (CQ and CQ) simplify data capture in high speed systems
- Data valid pin (QVLD) to indicate valid data on the output
- Synchronous internally self-timed writes
- DDR II+ operates with 2.0 cycle read latency when DOFF is asserted HIGH
