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Cypress Semiconductor Electronic Components Datasheet

CY7C1250KV18 Datasheet

36-Mbit DDR II+ SRAM Two-Word Burst Architecture

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CY7C1248KV18/CY7C1250KV18
36-Mbit DDR II+ SRAM Two-Word
Burst Architecture (2.0 Cycle Read Latency)
36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
Features
36-Mbit density (2M × 18, 1M × 36)
450 MHz clock for high bandwidth
Two-word burst for reducing address bus frequency
Double data rate (DDR) interfaces (data transferred at
900 MHz) at 450 MHz
Available in 2.0 clock cycle latency
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Data valid pin (QVLD) to indicate valid data on the output
Synchronous internally self-timed writes
DDR II+ operates with 2.0 cycle read latency when DOFF is
asserted HIGH
Operates similar to DDR I device with 1 cycle read latency when
DOFF is asserted LOW
Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD[1]
Supports both 1.5 V and 1.8 V I/O supply
HSTL inputs and variable drive HSTL output buffers
Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 compatible test access port
Phase-locked loop (PLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.0 Cycles:
CY7C1248KV18 – 2M × 18
CY7C1250KV18 – 1M × 36
Functional Description
The CY7C1248KV18, and CY7C1250KV18 are 1.8 V
synchronous pipelined SRAMs equipped with DDR II+
architecture. The DDR II+ consists of an SRAM core with
advanced synchronous peripheral circuitry. Addresses for read
and write are latched on alternate rising edges of the input (K)
clock. Write data is registered on the rising edges of both K and
K. Read data is driven on the rising edges of K and K. Each
address location is associated with two 18-bit words
(CY7C1248KV18), or 36-bit words (CY7C1250KV18) that burst
sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Maximum operating frequency
Maximum operating current
Description
450 MHz 400 MHz Unit
450 400 MHz
× 18 600
550 mA
× 36 760
690
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4 V to VDD.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-57834 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 16, 2016


Cypress Semiconductor Electronic Components Datasheet

CY7C1250KV18 Datasheet

36-Mbit DDR II+ SRAM Two-Word Burst Architecture

No Preview Available !

Logic Block Diagram – CY7C1248KV18
CY7C1248KV18/CY7C1250KV18
A(19:0)
20
LD
K
K
DOFF
VREF
R/W
BWS[1:0]
Address
Register
CLK
Gen.
Control
Logic
Write
Reg
Write
Reg
Read Data Reg.
36
18
18
18
Output
Logic
Control
R/W
Reg.
Reg.
Reg. 18
18
18
CQ
CQ
DQ[17:0]
QVLD
Logic Block Diagram – CY7C1250KV18
A(18:0)
19
LD
K
K
DOFF
VREF
R/W
BWS[3:0]
Address
Register
CLK
Gen.
Control
Logic
Document Number: 001-57834 Rev. *I
Write
Reg
Write
Reg
Read Data Reg.
72
36
36
36
Output
Logic
Control
R/W
Reg.
Reg.
Reg. 36
36
36
CQ
CQ
DQ[35:0]
QVLD
Page 2 of 29


Part Number CY7C1250KV18
Description 36-Mbit DDR II+ SRAM Two-Word Burst Architecture
Maker Cypress Semiconductor
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CY7C1250KV18 Datasheet PDF






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