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CY6264 - 8K x 8 Static RAM

General Description

The CY6264 is a high-performance CMOS static RAM organized as 8192 words by 8 bits.

Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state drivers.

Key Features

  • 55, 70 ns access times.
  • CMOS for optimum speed/power.
  • Easy memory expansion with CE1, CE2, and OE features.
  • TTL-compatible inputs and outputs.
  • Automatic power-down when deselected over 70% when deselected. The CY6264 is packaged in a 450-mil (300-mil body) SOIC. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE1 and WE inputs are both LOW and CE2 is HIGH, data on the eight data input/output pins (I/O.

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Other Datasheets by Cypress (now Infineon)

Part Number Description
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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1CY 626 4 PRELIMINARY CY6264 8K x 8 Static RAM Features • 55, 70 ns access times • CMOS for optimum speed/power • Easy memory expansion with CE1, CE2, and OE features • TTL-compatible inputs and outputs • Automatic power-down when deselected over 70% when deselected. The CY6264 is packaged in a 450-mil (300-mil body) SOIC. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE1 and WE inputs are both LOW and CE2 is HIGH, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A12).