CY62157DV30 Datasheet | Cypress

Features - Temperature ranges - Industrial: - 40 °C to 85 °C - Very high speed: 55 ns - Wide voltage range: 2.20 V- 3.60 V - Pin-patible with CY62157CV25, CY62157CV30, and CY62157CV33 - Ultra-low active power - Typical active current: 1.5 m A @ f = 1 MHz - Typical active current: 12 m A @ f = fmax - Ultra-low standby power - Easy memory expansion with CE1, CE2, and OE features - Automatic power-down when deselected - plementary metal oxide semiconductor (CMOS) for optimum speed/power - Available in Pb-free and non Pb-free 48-ball fine ball grid array (FBGA), and Pb-free 44-pin thin small outline package (TSOPII) package Functional Description The CY62157DV30 is a high-performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. Logic Block Diagram A10 A9 AAA876 A5 A4 A3 A2 AA01 DATA-IN DRIVERS 512K × 16 RAM Array COLUMN DECODER A11 A12 A13 A14 AAAA11118765 Power-down Circuit ROW DECODER SENSE AMPS This is ideal for providing More Battery Life (Mo BL®) in portable applications such as cellular telephones.The device also has an automatic power-down feature that significantly reduces power consumption. The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE LOW). Writing to the device is acplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A18). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the...