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CY62128 - 128K x 8 Static RAM

Download the CY62128 datasheet PDF. This datasheet also covers the CY6 variant, as both devices belong to the same 128k x 8 static ram family and are provided as variant models within a single manufacturer datasheet.

General Description

The CY62128 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits.

Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), an active LOW output enable (OE), and three-state drivers.

Key Features

  • 4.5V.
  • 5.5V operation.
  • CMOS for optimum speed/power.
  • Low active power (70 ns, LL version).
  • 330 mW (max. ) (60 mA).
  • Low standby power (70 ns, LL version).
  • 110 µW (max. ) (20 µA).
  • Automatic power-down when deselected.
  • TTL-compatible inputs and outputs.
  • Easy memory expansion with CE1, CE2, and OE options feature that reduces power consumption by more than 75% when deselected. Writing to the device is accomplishe.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY6-2128.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
CY62146DV30 4M Bit Static RAM Cypress
CY62146G 4-Mbit (256K words x 16 bit) Static RAM Cypress
CY62146G-MoBL 4-Mbit (256K words x 16 bit) Static RAM Cypress
CY62146GE 4-Mbit (256K words x 16 bit) Static RAM Cypress
CY62146GESL 4-Mbit (256K words x 16 bit) Static RAM Cypress

Other Datasheets by Cypress (now Infineon)

Part Number Description
CY621282BN 1-Mbit (128K x 8) Static RAM
CY62128B 128K x 8 Static RAM
CY62128BN 1-Mbit (128K x 8) Static RAM
CY62128DV30 1-Mb (128K x 8) Static RAM
CY62128E 1-Mbit (128K x 8) Static RAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
1CY 621 28 fax id: 1072 PRELIMINARY CY62128 128K x 8 Static RAM Features • 4.5V − 5.5V operation • CMOS for optimum speed/power • Low active power (70 ns, LL version) — 330 mW (max.) (60 mA) • Low standby power (70 ns, LL version) — 110 µW (max.) (20 µA) • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE1, CE2, and OE options feature that reduces power consumption by more than 75% when deselected. Writing to the device is accomplished by taking chip enable one (CE1) and write enable (WE) inputs LOW and chip enable two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16).