CY62128 Datasheet | Cypress

Features - 4.5V - 5.5V operation - CMOS for optimum speed/power - Low active power (70 ns, LL version) - 330 m W (max.) (60 m A) - Low standby power (70 ns, LL version) - 110 µW (max.) (20 µA) - Automatic power-down when deselected - TTL-patible inputs and outputs - Easy memory expansion with CE1, CE2, and OE options feature that reduces power consumption by more than 75% when deselected. Writing to the device is acplished by taking chip enable one (CE1) and write enable (WE) inputs LOW and chip enable two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is acplished by taking chip enable one (CE1) and output enable (OE) LOW while forcing write enable (WE) and chip enable two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY62128 is available in a standard 400-mil-wide SOJ, 525-mil wide (450-mil-wide body width) SOIC and 32-pin TSOP type I. Functional Description The CY62128 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), an active LOW output enable (OE), and three-state drivers. This device has an automatic power-down Logic Block Diagram Pin Configurations Top View SOJ / SOIC NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 I/O0 INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O1 I/O2 512 x 256 x 8 ARRAY I/O3 I/O4 I/O5 POWER DOWN A11 A9 A8...