CY37512VP352-83BGC Datasheet

Features and Benefits

• In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes
• High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated inputs including four clock pins
• Simple timing .