CY37384VP208-66NC
Description
The Ultra37000™ family of CMOS CPLDs provides a range of high-density programmable logic solutions with unparalleled system performance.
Key Features
- High density - 32 to 512 macrocells - 32 to 264 I/O pins - Five dedicated inputs including four clock pins
- Flexible clocking - Four synchronous clocks per device - Product term clocking - Clock polarity control per logic block
- Consistent package/pinout offering across all densities - Simplifies design migration - Same pinout for 3.3V and 5.0V devices
- Packages - 44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP, BGA, and Fine-Pitch BGA packages
