CY37064P84-200JC Overview
The Ultra37000™ family of CMOS CPLDs provides a range of high-density programmable logic solutions with unparalleled system performance. The Ultra37000 family is designed to bring the flexibility, ease of use, and performance of the 22V10 to high-density CPLDs. The architecture is based on a number of logic blocks that are connected by a Programmable Interconnect Matrix (PIM).
CY37064P84-200JC Key Features
- In-System Reprogrammable™ (ISR™) CMOS CPLDs
- JTAG interface for reconfigurability
- Design changes do not cause pinout changes
- Design changes do not cause timing changes
- High density
- 32 to 512 macrocells
- 32 to 264 I/O pins
- Five dedicated inputs including four clock pins
- Simple timing model
- No fanout delays