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CY37064P84-154JC Datasheet

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Cypress Semiconductor · CY37064P84-154JC File Size : 1.55MB · 4 hits

Features and Benefits


• In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes
• High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated inputs including four clock pins
• Simple timing .

CY37064P84-154JC CY37064P84-154JC CY37064P84-154JC
TAGS
5V
3V
ISR
High-Performance
CPLDs
CY37064P84-154JC
CY37064P84-154JI
CY37064P84-125JC
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