CY2DP1502 buffer equivalent, 1:2 lvpecl fanout buffer.
* One differential (LVPECL, LVDS, HCSL, or CML) input pair distributed to two LVPECL output pairs
* Translates any single-ended input signal to 3.3 V LVPECL level.
The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew.
The CY2DP1502 is an ultra-low noise, low-skew, low-propagation delay 1:2 LVPECL fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The device has a fully differential internal architecture that is optimized.
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