CY2210 Datasheet | Cypress

Features - Mixed 2.5V and 3.3V Operation - pliant to Intel® CK133 (CY2210-3) & CK133W (CY2210-2) synthesizer and driver specification - Multiple output clocks at different frequencies - Four CPU clocks, up to 133 MHz - Eight synchronous PCI clocks, 1 free-running - Two CPU/2 clocks, at one-half the CPU frequency - Four AGP clocks at 66 MHz - Three synchronous APIC clocks, at 16.67 MHz - One USB clock at 48 MHz - Two reference clocks at 14.318 MHz - Spread Spectrum clocking - 32.5-k Hz modulation frequency @ 133 MHz - 33.1-k Hz modulation frequency @ 100 MHz for CY2210-02/03 - 33.4-k Hz modulation frequency @ 100 MHz for CY2210-04 - EPROM programmable percentage of spreading. Default is - 0.6%, which is remended by Intel - Power-down features - Three Select inputs - Low-skew and low-jitter outputs - OE and Test Mode support - 56-pin SSOP package Benefits Usable with Pentium® II and Pentium® III processors Single-chip main motherboard clock generator - Driven together, support 4 CPUs and a chipset - Support for 4 PCI slots and chipset - Drives up to two main memory clock generators, including DRCG (CPUCLK/2) - Support for multiple AGP slots - Support multiprocessing systems - Supports USB frequencies and I/O chip Enables reduction of EMI in some systems Supports mobile systems Supports up to eight CPU clock frequencies Meets tight system timing requirements at high frequency Enables ATE and “bed of nails” testing Widely available, standard package enables lower cost Logic Block Diagram Pin Configuration SSOP Top View REFCLK [0- 1] (14.318 MHz) VSSREF REFCLK0 REFCLK1 VDDREF 1 2 3 4 5 6 7 8 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDAPIC APICCLK2 APICCLK1 APICCLK0 VSSAPIC VDDCPU/2 CPUCLK/2 (DRCG) CPUCLK/2 (DRCG) VSSCPU/2 VDDCPU CPUCLK3 CPUCLK2 VSSCPU VDDCPU CPUCLK1 CPUCLK0 VSSCPU AVDD AVSS PCI_STOP CPU_STOP PWR_DWN SPREAD SEL1 SEL0 VDDUSB USBCLK VSSUSB CPUCLK [0- 3] CPU_STOP XTALIN XTALOUT 14.318 MHz OSC. XTALIN XTALOUT...