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Cypress Semiconductor Electronic Components Datasheet

PLDC20G10 Datasheet

CMOS Generic 24-Pin Reprogrammable Logic Device

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PLDC20G10B
PLDC20G10
CMOS Generic 24-Pin Reprogrammable
Logic Device
Features
• Fast
— Commercial: tPD = 15 ns, tCO = 10 ns, tS = 12 ns
— Military: tPD = 20 ns, tCO = 15 ns, tS = 15 ns
• Low power
— ICC max.: 70 mA, commercial
— ICC max.: 100 mA, military
• Commercial and military temperature range
• User-programmable output cells
— Selectable for registered or combinatorial operation
— Output polarity control
— Output enable source selectable from pin 13 or
product term
• Generic architecture to replace standard logic
functions including: 20L10, 20L8, 20R8, 20R6, 20R4,
12L10, 14L8, 16L6, 18L4, 20L2, and 20V8
• Eight product terms and one OE product term per output
Logic Block Diagram
VSS I
II
12 11 10 9
II
87
• CMOS EPROM technology for reprogrammability
• Highly reliable
— Uses proven EPROM technology
— Fully AC and DC tested
— Security feature prevents logic pattern duplication
±10% power supply voltage and higher noise
immunity
Functional Description
Cypress PLD devices are high-speed electrically program-
mable logic devices. These devices utilize the sum-of-products
(AND-OR) structure providing users the ability to program
custom logic functions for unique requirements.
In an unprogrammed state the AND gates are connected via
EPROM cells to both the true and complement of every input.
By selectively programming the EPROM cells, AND gates may
be connected to either the true or complement or disconnected
from both true and complement inputs.
II
65
I I I CP/I
4 3 21
www.DataSheet.net/
PROGRAMMABLE
AND ARRAY
8 88 8 88 8 88 8
OUTPUT
CELL
OUTPUT
CELL
OUTPUT
CELL
OUTPUT
CELL
OUTPUT
CELL
OUTPUT
CELL
OUTPUT
CELL
OUTPUT
CELL
OUTPUT
CELL
OUTPUT
CELL
13 14 15 16 17 18 19
20 21 22 23 24
I/OE
I/O 9
I/O 8
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
V CC
Pin Configurations
LCC
Top View
STD PLCC
Top View
JEDEC PLCC [1]
Top View
4 3 2 1 282726
I5
25 NC
I6
24 I/O 2
I
I
I
7
8
9
PLDC20G10
PLDC20G10B
23
22
21
I/O 3
I/O 4
I/O 5
I 10
20 I/O 6
NC 11
19 I/O 7
12131415161718
4 3 2 1 2827 26
NC 5
25 I/O 2
I6
24 I/O3
I 7 PLDC20G10 23 I/O 4
NC 8 PLDC20G10B 22 I/O5
I9
21 I/O 6
I 10
20 I/O7
NC 11 121314 1516 171819 NC
4 3 2 1 2827 26
I5
25
I6
24
I
NC
7
8
CG7C323–A 23
CG7C323B–A 22
I9
21
I 10
20
I 11 121314 1516 171819
I/O2
I/O3
I/O4
NC
I/O5
I/O 6
I/O 7
Note:
1. The CG7C323 is the PLDC20G10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts. The
difference is in the location of the “no connect” or NC pins.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-03010 Rev. *A
Revised April 20, 2004
Datasheet pdf - http://www.DataSheet4U.co.kr/


Cypress Semiconductor Electronic Components Datasheet

PLDC20G10 Datasheet

CMOS Generic 24-Pin Reprogrammable Logic Device

No Preview Available !

USE ULTRA37000™ FOR
ALL NEW DESIGNS
PLDC20G10B
PLDC20G10
Selection Guide
Generic
Part Number
20G10B–15
20G10B–20
20G10B–25
20G10–25
20G10–30
20G10–35
20G10–40
ICC (mA)
Com/Ind
70
70
55
55
Mil
100
100
80
80
tPD (ns)
Com/Ind
15
20
25
35
Mil
20
25
30
40
tS (ns)
Com/Ind
12
12
15
30
Mil
15
18
20
35
tCO (ns)
Com/Ind
10
12
15
25
Mil
15
15
20
25
Functional Description
Cypress PLDC20G10 uses an advanced 0.8-micron CMOS
technology and a proven EPROM cell as the programmable
element. This technology and the inherent advantage of being
able to program and erase each cell enhances the reliability
and testability of the circuit. This reduces the burden on the
customer to test and to handle rejects.
A preload function allows the registered outputs to be preset
to any pattern during testing. Preload is important for testing
the functionality of the Cypress PLD device.
20G10 Functional Description
The PLDC20G10 is a generic 24-pin device that can be
programmed to logic functions that include but are not limited
to: 20L10, 20L8, 20R8, 20R6, 20R4, 12L10, 14L8, 16L6, 18L4,
20L2, and 20V8. Thus, the PLDC20G10 provides significant
design, inventory and programming flexibility over dedicated
24-pin devices. It is executed in a 24-pin 300-mil molded DIP
and a 300-mil windowed cerDIP. It provides up to 22 inputs and
10 outputs. When the windowed cerDIP is exposed to UV light,
the 20G10 is erased and then can be reprogrammed.
The programmable output cell provides the capability of
defining the architecture of each output individually. Each of
the 10 output cells may be configured with registered or combi-
natorial outputs, active HIGH or active LOW outputs, and
product term or Pin 13 generated output enables. Three archi-
tecture bits determine the configurations as shown in the
Configuration Table and in Figures 1 through 8. A total of eight
different configurations are possible, with the two most
common shown in Figure 3 and Figure 5. The default or unpro-
grammed state is registered/active/LOW/Pin 11 OE. The
entire programmable output cell is shown in the next section.
The architecture bit ‘C1’ controls the registered/combinatorial
option. In either combinatorial or registered configuration, the
output can serve as an I/O pin, or if the output is disabled, as
an input only. Any unused inputs should be tied to ground. In
either registered or combinatorial configuration, the output of
the register is fed back to the array. This allows the creation of
control-state machines by providing the next state. The
register is clocked by the signal from Pin 1. The register is
initialized on power up to Q output LOW and Q output HIGH.
In both the combinatorial and registered configurations, the
source of the output enable signal can be individually chosen
www.DataSheet.net/
with architecture bit ‘C2’. The OE signal may be generated
within the array, or from the external OE (Pin 13). The Pin 13
allows direct control of the outputs, hence having faster
enable/disable times.
Each output cell can be configured for output polarity. The
output can be either active HIGH or active LOW. This option is
controlled by architecture bit ‘C0’.
Along with this increase in functional density, the Cypress
PLDC20G10 provides lower-power operation through the use
of CMOS technology and increased testability with a register
preload feature.
Document #: 38-03010 Rev. *A
Page 2 of 14
Datasheet pdf - http://www.DataSheet4U.co.kr/


Part Number PLDC20G10
Description CMOS Generic 24-Pin Reprogrammable Logic Device
Maker Cypress
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PLDC20G10 Datasheet PDF






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