CY7C1373C
Key Features
- No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
- Can support up to 133-MHz bus operations with zero wait states - Data is transferred on every clock
- Internally self-timed output buffer control to eliminate the need to use OE
- Registered inputs for flow-through operation
- 3.3V/2.5V I/O power supply
- Fast clock-to-output times - 6.5 ns (for 133-MHz device) - 7.5 ns (for 117-MHz device) - 8.5 ns (for 100-MHz device)
- Clock Enable (CEN) pin to enable clock and suspend operation
- Synchronous self-timed writes
- Asynchronous Output Enable
- Offered in JEDEC-standard 100 TQFP, 119-Ball BGA and 165-Ball fBGA packages
