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Cypress Semiconductor Electronic Components Datasheet

CY7C1373C Datasheet

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture

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CY7C1371C
CY7C1373C
18-Mbit (512K x 36/1M x 18) Flow-Through
SRAM with NoBL™ Architecture
Features
Functional Description[1]
• No Bus Latency™ (NoBL™) architecture eliminates
dead cycles between write and read cycles
• Can support up to 133-MHz bus operations with zero
wait states
— Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 3.3V/2.5V I/O power supply
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 7.5 ns (for 117-MHz device)
— 8.5 ns (for 100-MHz device)
• Clock Enable (CEN) pin to enable clock and suspend
operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• Offered in JEDEC-standard 100 TQFP, 119-Ball BGA and
165-Ball fBGA packages
• Three chip enables for simple depth expansion
• Automatic Power-down feature available using ZZ
mode or CE deselect
• JTAG boundary scan for BGA and fBGA packages
• Burst Capability—linear or interleaved burst order
• Low standby power
The CY7C1371C/CY7C1373C is a 3.3V, 512K x 36/ 1M x 18
Synchronous Flow-through Burst SRAM designed specifically
to support unlimited true back-to-back Read/Write operations
without the insertion of wait states. The CY7C1371C/
CY7C1373C is equipped with the advanced No Bus Latency™
(NoBL™) logic required to enable consecutive Read/Write
operations with data being transferred on every clock cycle.
This feature dramatically improves the throughput of data
through the SRAM, especially in systems that require frequent
Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two or four Byte Write
Select (BWX) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
Selection Guide
133 MHz
117 MHz
100 MHz
Maximum Access Time
6.5 7.5 8.5
Maximum Operating Current
210 190 175
Maximum CMOS Standby Current 70 70 70
Notes:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05234 Rev. *D
Revised June 03, 2004


Cypress Semiconductor Electronic Components Datasheet

CY7C1373C Datasheet

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture

No Preview Available !

1
Logic Block Diagram – CY7C1371C (512K x 36)
A0, A1, A
MODE
CLK C
CEN
CE
ADDRESS
REGISTER
A1
A0
D1
D0
ADV/LD
C
WRITE ADDRESS
REGISTER
Q1
Q0
A1'
A0'
BURST
LOGIC
ADV/LD
BWA
BWB
BWC
BWD
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
OE
CE1
READ LOGIC
CE2
CE3
ZZ
SLEEP
CONTROL
INPUT E
REGISTER
CY7C1371C
CY7C1373C
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
NE
G
DQs
DQPA
DQPB
DQPC
DQPD
2
Logic Block Diagram – CY7C1373C (1M x 18)
A0, A1, A
MODE
CLK C
CEN
CE
ADDRESS
REGISTER
A1
A0
D1
D0
ADV/LD
C
WRITE ADDRESS
REGISTER
Q1
Q0
A1'
A0'
BURST
LOGIC
ADV/LD
BWA
BWB
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
OE
CE1
CE2
CE3
ZZ
3
Document #: 38-05234 Rev. *D
READ LOGIC
SLEEP
CONTROL
INPUT E
REGISTER
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
NE
G
DQs
DQPA
DQPB
Page 2 of 33


Part Number CY7C1373C
Description 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture
Maker Cypress
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CY7C1373C Datasheet PDF






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