CS6403 Datasheet | Cirrus Logic

Features Description The CS6403 is an application-specific digital signal processor optimized for network and acoustic echo cancellation applications. A high-quality codec is integrated with the processor to provide a plete, lowcost echo-cancellation solution. The CS6403 is a fully independent processor that requires no signal processing support to implement its cancellation functions. Volume control, AGC, and sleep functions are also provided. The on-chip ADC and DAC employ over-sampling technology, which eliminates the need for plex external anti-aliasing and reconstruction filters, further reducing system cost. The CS6403 has a serial interface that is patible with most DSPs and PCM codecs. Clock and sync lines control the transfer of serial data via the separate serial datain and data-out pins. Both 16-bit audio data and control/status information may be multiplexed on this serial channel using a steering bit. ORDERING INFORMATION CS6403-IQ -40° to +85° C 44-pin TQFP CS6403-IL -40° to +85° C 44-pin PLCC CDB6403 Evaluation Board l Applicable in: Digital-Cellular Hands-Free Phones Analog-Cellular Hands-Free Phones Office Speaker Phones Desktop & Video Teleconferencing l Echo Cancellation l Serial Data/Control Interface l On-Chip Delta-Sigma Codec - - Up to 60 d B ERLE - 512 Tap (64 ms at 8 k Hz sampling rate) - Split Mode For Two Echo Cancellers l Automatic Gain Control (AGC) l No Training Signals Generated < 1% THD, 8 Ω Load On Output > 70 d B S/(N+D) on Input 300-3600 Hz Bandwidth (8 k Hz sampling rate) Volume Control Microphone Preamp DVDD0 CONFIG GPIN0 GPIN1 GPIN2 GPIN3 GPOUT0 GPOUT1 SFRAME SMASTER UALAW SSYNC SCLK SDO_1 SDI_A SYNCOUT Serial I/O RESERVED0 AVDD RESET DSP High Pass Control Status Control A Nonlinear Volume Echo G Control C Control Echo Cancellers Nonlinear Echo Control PLL + Clock Manager DGND0 1 High Pass A T T E N A T T E N Analog I/O D/A PVDD SPKROUTP SPKROUTN PGND0 PGND1 26 d B A/D MICIN VCM VREF 1 NC CLKIN CLKOUTSCLK_RATE0SCL...