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CS5542 Datasheet Preview

CS5542 Datasheet

Multi-Channel DS ADC

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CS5542
CS5543
22-Bit, Multi-Channel ∆Σ ADC Chip Set
Features
l Delta-Sigma Architecture:
- 5th Order Modulator
- 22-Bit Resolution
l dc Accuracy (fBW = 250Hz):
- Integral Linearity: ±0.001 % F.S.
www.DataSheet4U- .cDomifferential Linearity: ±0.5 LSBs
- RMS Noise: 1.1 pARMS
l Pin Selectable Input Range:
- ±400 nA to ±2.5 µA Full Scale
l 8-Channel Digital FIR Filter
l Self-calibration of Offset and Gain
l Low Power: 50 mW /ch for 8-ch system
Description
The CS5542 / CS5543 chip set is designed to be a com-
plete current measurement data acquisition system.
The CS5542 is a 22-Bit, 2-channel, 5th-order delta sig-
ma modulator. The CS5543 is a monolithic CMOS, 8-
channel digital FIR filter designed to be used with up to
four CS5542’s forming an 8-channel system. The com-
plete system is capable of cascading up to 1024
channels.
The system supports 22-bit measurement resolution
with output conversion rates up to 1 kHz per channel.
JTAG boundary-scan capability is available to facilitate
self-test at the system level.
Potential applications for the CS5542/CS5543 system
are environmental monitoring, process control systems,
color sensing, light measurement, chemical analyzers
and photo-diode transducer applications.
ORDERING INFORMATION
CS5542-KL 0 to 70°C
CS5543-KL 0 to 70°C
28-pin PLCC
28-pin PLCC
VD1+GND1VD2+GND2VD3+GND3
REFGNDL
INL
ICAL
INR
REFGNDR
VA+ VA- GNDL VD+ DGND
5th Order
Delta-Sigma
Modulator
Left
Channel
ICAL Bias
MUX Regulator
5th Order
Delta-Sigma
Modulator
Right
Channel
Calibra-
tion
and
Digital
Control
Logic
VREF+ VREF- GNDR SEL0SEL1
CS5542
CAPSIZE
MCLK
FSYNC
PDN
C[2.0]
CAL[1:0]
3
2
Control/Sequencing
CAPSIZE
TCK
TMS
TDI
Test
Access
TDO Port
PDN
MCLK
FSYNC
CAL[1:0]
MDATA
[3:0]
4
MDATA[3:0]
C[2:0]
DATACLK
FRAME
Serial I/O
CS5543
3 DMODE[2:0]
RST
CLKIN
FEGAIN
OE
4 DATSEL[3:0]
4 DATAIN[3:0]
4
DATAOUT
[3:0]
Preliminary Product Information
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 1997
(All Rights Reserved)
SEP ‘96
DS109PP2
1




Cirrus Logic

CS5542 Datasheet Preview

CS5542 Datasheet

Multi-Channel DS ADC

No Preview Available !

CS5542 CS5543
ANALOG CHARACTERISTICS: (TA = 25° C; VA+, VD+ = 5 V ±5%; VA- = -5 V ±5%; GNDL,GNDR,
& DGND= 0V;VREF+ = 4V, VREF- = -4 V; MCLK frequency as noted.)
Parameter
Min Typ Max Units
Specified Temperature Range
Accuracy
Full Scale Input Current (Bipolar)
CAPSIZE=0
CAPSIZE=1
(Note 1)
(Note 1)
Dynamic Range
www.DataSheet4U.com
CAPSIZE=0
CAPSIZE=1
(Note 1)
(Note 1)
Differential Nonlinearity (No Missing Codes) (Note 2)
Integral Nonlinearity
(Note 1)
Full Scale Error
(Note 3)
Full Scale Drift
(Note 3)
System Offset Calibration Range
(Note 4)
Offset Drift
(Note 1)
Power Supplies
(Note 5)
Consumption
Active
Powerdown
50, 60 Hz Power Supply Rejection: VA+ or VA- (Notes 1, 6)
Fullscale Current = 400 nA
60 Hz
500 Hz
Fullscale Current = 2500 nA
60 Hz
500 Hz
0
-
-
106
113
22
-
-
-
-
-
-
-
-
-
-
-
-
- 70 °C
400
2500
109
116
-
-
-
30
-
±0.3
-
-
-
-
-
0.001
0.1
-
10
-
nA
nA
dB
dB
Bits
%FS
%FS
ppm/°C
%FS
LSB/°C
-
-
TBD
1.85
13.5
1.88
15.3
80 mW
10 mW
- dB
- nA/V
- nA/V
- nA/V
- nA/V
Notes: 1. Full scale current is tested under two conditions: CAPSIZE = 0 (CDAC = 1.6 pF) with MCLK at 1.024
MHz and CAPSIZE = 1 (CDAC = 4.8 pF) with MCLK at 2.048 MHz. Dynamic Range (Signal-to-Noise) is
tested with 101 Hz sine wave voltage driven into a 5 Minput resistor with a 470 pF capacitor connected
from INR or INL to REFGNDR or REFGNDL respectively, to test each modulator. S/N and integral
nonlinearity are tested with CAPSIZE = 0 (CDAC = 1.6 pF) with MCLK at 2.048 MHz and CAPSIZE = 1
(CDAC = 4.8 pF) with MCLK at 1.024 MHz.
2. Guaranteed by design or characterization.
3. Specification applies after a complete calibration sequence using the CS5542/CS5543 combination. Drift
specification is for the CS5542/CS5543 only and does not include drift due to the input components, the
VREF voltage, or a frequency change of CLKIN.
4. Specification applies only to System Offset Calibration using the CS5542/CS5543 chip combination after
Input Offset Voltage calibration has been completed with no external offset applied to the input.
5. The VA+ and VA- supplies should be quiet supplies (see data sheet text). Power supply sequence is
important. The VA+ and VA- supplies should be applied to the CS5542 prior to or at the same time as
the VD+ supply.
6. Power supply rejection is tested with a 100 mVp-p sine wave applied to each supply. See data sheet
text for power supply noise requirements.
2 DS109PP2


Part Number CS5542
Description Multi-Channel DS ADC
Maker Cirrus Logic
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CS5542 Datasheet PDF






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