CS5533 Datasheet | Cirrus Logic

CS5531/32/33/34 16-Bit and 24-Bit ADCs with Ultra Low Noise PGIA Features Chopper Stabilized PGIA (Programmable Gain Instrumentation Amplifier, 1x to 64x) 6 n V/√Hz @ 0.1 Hz (No 1/f noise) at 64x 500 p A Input Current with Gains >1 Delta-Sigma Analog-to-Digital Converter Linearity Error: 0.0007% FS Noise Free Resolution: Up to 23 bits Two or Four Channel Differential MUX Scalable Input Span via Calibration ±5 m V to differential ±2.5V Scalable VREF Input: Up to Analog Supply Simple three-wire serial interface SPI®and Microwire™ patible Schmitt Trigger on Serial Clock (SCLK) R/W Calibration Registers Per Channel Selectable Word Rates: 6.25 to 3,840 Sps Selectable 50 or 60 Hz Rejection Power Supply Configurations VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V VA+ = +3 V; VA- = -3 V; VD+ = +3 V General Description The CS5531/32/33/34 are highly integrated ∆Σ Analogto-Digital Converters (ADCs) which use charge-balance techniques to achieve 16-bit (CS5531/33) and 24-bit (CS5532/34) performance. The ADCs are optimized for measuring low-level unipolar or bipolar signals in weigh scale, process control, scientific, and medical applications. To acmodate these applications, the ADCs e as either two-channel (CS5531/32) or four-channel (CS5533/34) devices and include a very low noise chopper-stabilized instrumentation amplifier (6 n V/√Hz @ 0.1 Hz) with selectable gains of 1×, 2×, 4×, 8×, 16×, 32×, and 64×. These ADCs also include a fourth order ∆Σ modulator followed by a digital filter which provides twenty selectable output word rates of 6.25, 7.5, 12.5, 15, 25, 30, 50, 60, 100, 120, 200, 240, 400, 480, 800, 960, 1600, 1920, 3200, and 3840 Sps (MCLK = 4.9152 MHz). To ease munication between the ADCs and a microcontroller, the converters include a simple three-wire serial interface which is SPI and Microwire patible with a Schmitt Trigger input on the serial clock (SCLK). High dynamic range, programmable output rates,...