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Cirrus Logic

CS5523 Datasheet Preview

CS5523 Datasheet

ADC

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CS5521/22/23/24/28
16-bit or 24-bit, 2/4/8-channel ADCs with PGIA
Features
Low Input Current (100 pA), Chopper-
stabilized Instrumentation Amplifier
Scalable Input Span (Bipolar/Unipolar)
- 2.5V VREF: 25 mV, 55 mV, 100 mV, 1 V,
2.5 V, 5 V
- External: 10 V, 100 V
Wide VREF Input Range (+1 to +5 V)
Fourth Order Delta-Sigma A/D Converter
Easy to Use Three-wire Serial Interface Port
- Programmable/Auto Channel Sequencer with
Conversion Data FIFO
- Accessible Calibration Registers per Channel
- Compatible with SPI™ and Microwire™
System and Self Calibration
Eight Selectable Word Rates
- Up to 617 Sps (XIN = 200 kHz)
- Single Conversion Settling
- 50/60 Hz ±3 Hz Simultaneous Rejection
Single +5 V Power Supply Operation
- Charge Pump Drive for Negative Supply
- +3 to +5 V Digital Supply Operation
Low Power Consumption: 6.0 mW
General Description
The CS5521/22/23/24/28 are highly integrated ΔΣ ana-
log-to-digital converters (ADCs) which use charge-
balance techniques to achieve 16-bit (CS5521/23) and
24-bit (CS5522/24/28) performance. The ADCs come as
either two-channel (CS5521/22), four-channel
(CS5523/24), or eight-channel (CS5528) devices and
include a low-input-current, chopper-stabilized instru-
mentation amplifier. To permit selectable input spans of
25 mV, 55 mV, 100 mV, 1 V, 2.5 V, and 5 V, the ADCs
include a PGA (programmable gain amplifier). To ac-
commodate ground-based thermocouple applications,
the devices include a charge pump drive which provides
a negative bias voltage to the on-chip amplifiers.
These devices also include a fourth-order ΔΣ modulator
followed by a digital filter which provides eight selectable
output word rates. The digital filters are designed to settle
to full accuracy within one conversion cycle and when
operated at word rates below 30 Sps, they reject both
50 Hz and 60 Hz interference.
These single-supply products are ideal solutions for
measuring isolated and non-isolated, low-level signals in
process control applications.
ORDERING INFORMATION
See page 53.
AIN1+
AIN1-
AIN2+
AIN2-
AIN3+
AIN3-
AIN4+
AIN4-
NBV
MUX
CS5524
Shown
VA+ AGND VREF+ VREF-
DGND VD+
X1
+
X20
X1
X1
Differential
4th Order
ΔΣ
Modulator
Digital Filter
Controller,
Setup Registers,
&
Channel Scan
Logic
Latch
Clock
Gen.
Data FIFO &
Calibration Registers
Serial Port
Interface
CPD
A0 A1 XIN XOUT
CS
SCLK
SDI
SDO
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2009
(All Rights Reserved)
JUL ‘09
DS317F8




Cirrus Logic

CS5523 Datasheet Preview

CS5523 Datasheet

ADC

No Preview Available !

CS5521/22/23/24/28
TABLE OF CONTENTS
ANALOG CHARACTERISTICS ................................................................................................ 5
TYPICAL RMS NOISE, CS5521/23.......................................................................................... 7
TYPICAL NOISE FREE RESOLUTION (BITS), CS5521/23 .................................................... 7
TYPICAL RMS NOISE, CS5522/24/28..................................................................................... 8
TYPICAL NOISE FREE RESOLUTION (BITS), CS5522/24/28 ............................................... 8
5 V DIGITAL CHARACTERISTICS........................................................................................... 9
3 V DIGITAL CHARACTERISTICS........................................................................................... 9
DYNAMIC CHARACTERISTICS ............................................................................................ 10
RECOMMENDED OPERATING CONDITIONS ..................................................................... 10
ABSOLUTE MAXIMUM RATINGS ......................................................................................... 10
SWITCHING CHARACTERISTICS ........................................................................................ 11
1. GENERAL DESCRIPTION ..................................................................................................... 13
1.1 Analog Input ..................................................................................................................... 13
1.1.1 Instrumentation Amplifier ......................................................................................... 14
1.1.2 Coarse/Fine Charge Buffers ............................................................................... 14
1.1.3 Analog Input Span Considerations .......................................................................... 15
1.1.4 Measuring Voltages Higher than 5 V .................................................................. 15
1.1.5 Voltage Reference .............................................................................................. 16
1.2 Overview of ADC Register Structure and Operating Modes ............................................ 16
1.2.1 System Initialization ............................................................................................ 18
1.2.2 Command Register Quick Reference ............................................................... 19
1.2.3 Command Register Descriptions ........................................................................ 20
1.2.4 Serial Port Interface ............................................................................................ 25
1.2.5 Reading/Writing the Offset, Gain, and Configuration Registers .......................... 26
1.2.6 Reading/Writing the Channel-Setup Registers ................................................... 26
1.2.6.1 Latch Outputs ...................................................................................... 28
1.2.6.2 Channel Select Bits ............................................................................. 28
1.2.6.3 Output Word Rate Selection ............................................................... 28
1.2.6.4 Gain Bits .............................................................................................. 28
1.2.6.5 Unipolar/Bipolar Bit ............................................................................. 28
1.2.7 Configuration Register ........................................................................................ 28
1.2.7.1 Chop Frequency Select ....................................................................... 28
1.2.7.2 Conversion/Calibration Control Bits .................................................... 28
1.2.7.3 Power Consumption Control Bits ........................................................ 28
1.2.7.4 Charge Pump Disable ......................................................................... 29
1.2.7.5 Reset System Control Bits .................................................................. 29
1.2.7.6 Data Conversion Error Flags ............................................................... 29
1.3 Calibration ........................................................................................................................ 31
1.3.1 Self Calibration .................................................................................................... 31
1.3.2 System Calibration .............................................................................................. 32
1.3.3 Calibration Tips ................................................................................................... 34
1.3.4 Limitations in Calibration Range ......................................................................... 34
1.4 Performing Conversions and Reading the Data Conversion FIFO .................................. 34
1.4.1 Conversion Protocol ............................................................................................ 35
1.4.1.1 Single, One-Setup Conversion ............................................................ 35
1.4.1.2 Repeated One-Setup Conversions without Wait ................................. 35
1.4.1.3 Repeated One-Setup Conversions with Wait ...................................... 36
1.4.1.4 Single, Multiple-Setup Conversions .................................................... 36
1.4.1.5 Repeated Multiple-Setup Conversions without Wait ........................... 37
1.4.1.6 Repeated Multiple-Setup Conversions with Wait ................................ 37
1.4.2 Calibration Protocol ............................................................................................. 38
2 DS317F8


Part Number CS5523
Description ADC
Maker Cirrus Logic
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CS5523 Datasheet PDF






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