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Cirrus Logic

CS5346 Datasheet Preview

CS5346 Datasheet

Stereo Audio ADC

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CS5346
103-dB, 192-kHz, Stereo Audio ADC with 6:1 Input Mux
ADC Features
Multi-bit Delta–Sigma Modulator
103 dB Dynamic Range
-95 dB THD+N
Stereo 6:1 Input Multiplexer
Programmable Gain Amplifier (PGA)
– ± 12 dB Gain, 0.5-dB Step Size
– Zero-crossing, Click-free Transitions
Stereo Microphone Inputs
– +32 dB Gain Stage
– Low-noise Bias Supply
Up to 192 kHz Sampling Rates
Selectable 24-bit, Left-justified or I²S Serial
Audio Interface Formats
System Features
Power-down Mode
+5 V Analog Power Supply, Nominal
+3.3 V Digital Power Supply, Nominal
Direct Interface with 3.3 V to 5 V Logic Levels
Pin Compatible with CS5345 (*See Section 2
for details.)
General Description
The CS5346 integrates an analog multiplexer, program-
mable gain amplifier, and stereo audio analog-to-digital
converter. The CS5346 performs stereo analog-to-digi-
tal (A/D) conve rsion of 24-bit serial values at sa mple
rates up to 192 kHz.
A 6:1 stereo input multiplexer is included for selecting
between line-level and microphone-level inputs. The
microphone input path includes a +32 dB gain stage
and a low-noise bias voltage supply. The PGA is avail-
able for line or microphone inputs and provides
gain/attenuation of ±12 dB in 0.5 dB steps.
The output of the PGA is followed by an advanced 5th-
order, multi-bit delta-sigma modulator and digital filter-
ing/decimation. Sampled data is transmitted by the
serial audio interface at rates from 8 kHz to 192 kHz in
either Slave or Master Mode.
Integrated level translators allow easy interfacing be-
tween the CS5346 and other devices operating over a
wide range of logic levels.
The CS5346 is available in a 48-pin LQFP package in
Commercial (-40° to +85° C) grade. The CDB5346 Cus-
tomer Demonstration board is also available for device
evaluation and implementation suggestions. Please re-
fer to “Ordering Information” on page 38 for complete
details.
3.3 V to 5 V
I²C/SPI
Control Data
Interrupt
Overflow
Reset
Serial
Audio
Output
3.3 V
Register Configuration
High Pass
Filter
Low-Latency
Anti-Alias Filter
High Pass
Filter
Low-Latency
Anti-Alias Filter
5V
Internal Voltage
Reference
Multibit
Oversampling
ADC
Multibit
Oversampling
ADC
PGA
MUX
PGAA
+32 dB
+32 dB
Left PGA Output
Right PGA Output
Stereo Input 1
Stereo Input 2
Stereo Input 3
Stereo Input 4 /
Mic Input 1 & 2
Stereo Input 5
Stereo Input 6
Preliminary Product Information
This document contains information for a product under development.
Cirrus Logic reserves the right to modify this product without notice.
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2012
(All Rights Reserved)
AUG ‘12
DS861PP3




Cirrus Logic

CS5346 Datasheet Preview

CS5346 Datasheet

Stereo Audio ADC

No Preview Available !

CS5346
TABLE OF CONTENTS
1. PIN DESCRIPTIONS - CS5346 ............................................................................................................. 5
2. PIN COMPATIBILITY - CS5345/CS5346 DIFFERENCES ..................................................................... 7
3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8
RECOMMENDED OPERATING CONDITIONS ................................................................................... 8
ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 8
ANALOG CHARACTERISTICS ............................................................................................................ 9
ANALOG CHARACTERISTICS CONT. .............................................................................................. 10
DIGITAL FILTER CHARACTERISTICS .............................................................................................. 11
DC ELECTRICAL CHARACTERISTICS ............................................................................................. 12
DIGITAL INTERFACE CHARACTERISTICS ...................................................................................... 13
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ............................................................. 14
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT ............................................ 16
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ........................................... 17
4. TYPICAL CONNECTION DIAGRAM ................................................................................................... 18
5. APPLICATIONS ................................................................................................................................... 19
5.1 Recommended Power-Up Sequence ............................................................................................. 19
5.2 System Clocking ............................................................................................................................. 19
5.2.1 Master Clock ......................................................................................................................... 19
5.2.2 Master Mode ......................................................................................................................... 20
5.2.3 Slave Mode ........................................................................................................................... 20
5.3 High-Pass Filter and DC Offset Calibration .................................................................................... 20
5.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................................ 21
5.5 Input Connections ........................................................................................................................... 21
5.5.1 Analog Input Configuration for 1 VRMS Input Levels ............................................................ 21
5.5.2 Analog Input Configuration for 2 VRMS Input Levels ............................................................ 22
5.6 PGA Auxiliary Analog Output ......................................................................................................... 23
5.7 Control Port Description and Timing ............................................................................................... 23
5.7.1 SPI Mode ............................................................................................................................... 23
5.7.2 I²C Mode ................................................................................................................................ 24
5.8 Interrupts and Overflow .................................................................................................................. 25
5.9 Reset .............................................................................................................................................. 26
5.10 Synchronization of Multiple Devices ............................................................................................. 26
5.11 Grounding and Power Supply Decoupling .................................................................................... 26
6. REGISTER QUICK REFERENCE ........................................................................................................ 27
7. REGISTER DESCRIPTION .................................................................................................................. 28
7.1 Chip ID - Register 01h .................................................................................................................... 28
7.2 Power Control - Address 02h ......................................................................................................... 28
7.2.1 Freeze (Bit 7) ......................................................................................................................... 28
7.2.2 Power-Down MIC (Bit 3) ........................................................................................................ 28
7.2.3 Power-Down ADC (Bit 2) ....................................................................................................... 28
7.2.4 Power-Down Device (Bit 0) ................................................................................................... 28
7.3 ADC Control - Address 04h ............................................................................................................ 29
7.3.1 Functional Mode (Bits 7:6) .................................................................................................... 29
7.3.2 Digital Interface Format (Bit 4) .............................................................................................. 29
7.3.3 Mute (Bit 2) ............................................................................................................................ 29
7.3.4 High-Pass Filter Freeze (Bit 1) .............................................................................................. 29
7.3.5 Master / Slave Mode (Bit 0) ................................................................................................... 29
7.4 MCLK Frequency - Address 05h .................................................................................................... 30
7.4.1 Master Clock Dividers (Bits 6:4) ............................................................................................ 30
7.5 PGAOut Control - Address 06h ...................................................................................................... 30
7.5.1 PGAOut Source Select (Bit 6) ............................................................................................... 30
7.6 Channel B PGA Control - Address 07h .......................................................................................... 30
2 DS861PP3


Part Number CS5346
Description Stereo Audio ADC
Maker Cirrus Logic
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CS5346 Datasheet PDF






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