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CS2501 - Fractional-N Clock Multiplier

General Description

The CS2501 is a system-clocking device incorporating a programmable phase-locked loop (PLL).

The hybrid analog/ digital PLL architecture comprises a delta-sigma fractional-N analog PLL and a digital frequency-locked loop (FLL).

Key Features

  • I²C/SPI control port.
  • Fractional clock multiplier and jitter reduction using hybrid analog/digital PLL.
  • Generates low-jitter 6.
  • 75 MHz clock (CLK_OUT), synchronized to a 50 Hz.
  • 30 MHz low-quality or intermittent frequency reference (CLK_IN).
  • Flexible timing reference source.
  • External clock, external crystal, or built-in oscillator.
  • Configurable auxiliary clock/status output.
  • Minimal board space required.
  • No.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CS2501 Fractional-N Clock Multiplier Features • I²C/SPI control port • Fractional clock multiplier and jitter reduction using hybrid analog/digital PLL — Generates low-jitter 6–75 MHz clock (CLK_OUT), synchronized to a 50 Hz–30 MHz low-quality or intermittent frequency reference (CLK_IN) • Flexible timing reference source — External clock, external crystal, or built-in oscillator • Configurable auxiliary clock/status output • Minimal board space required — No external analog loop-filter components • Pin-to-pin, register map, and control compatible with CS2100 and CS2300 • Single-supply operation at 1.8 V or 3.