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CS2300-CP - Fractional-N Clock Multiplier

General Description

The CS2300-CP is an extremely versatile system clocking device that utilizes a programmable phase lock loop.

The CS2300-CP is based on a hybrid analog-digital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital PLL.

Key Features

  •  Clock Multiplier / Jitter Reduction.
  • Generates a Low Jitter 6 - 75 MHz Clock from a Jittery or Intermittent 50 Hz to 30 MHz Clock Source  Internal LC Oscillator for Timing Reference  Highly Accurate PLL Multiplication Factor.
  • Maximum Error less than 1 PPM in HighResolution Mode  I²C / SPI™ Control Port  Configurable Auxiliary Output  Minimal Board Space Required.
  • No External Analog Loop-filter Components General.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CS2300-CP Fractional-N Clock Multiplier with Internal LCO Features  Clock Multiplier / Jitter Reduction – Generates a Low Jitter 6 - 75 MHz Clock from a Jittery or Intermittent 50 Hz to 30 MHz Clock Source  Internal LC Oscillator for Timing Reference  Highly Accurate PLL Multiplication Factor – Maximum Error less than 1 PPM in HighResolution Mode  I²C / SPI™ Control Port  Configurable Auxiliary Output  Minimal Board Space Required – No External Analog Loop-filter Components General Description The CS2300-CP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2300-CP is based on a hybrid analog-digital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital PLL.