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Cirrus Logic

CS2000-CP Datasheet Preview

CS2000-CP Datasheet

Fractional-N Clock Synthesizer & Clock Multiplier

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CS2000-CP
Fractional-N Clock Synthesizer & Clock Multiplier
Features
Delta-Sigma Fractional-N Frequency Synthesis
– Generates a Low Jitter 6 - 75 MHz Clock
from an 8 - 75 MHz Reference Clock
Clock Multiplier / Jitter Reduction
– Generates a Low Jitter 6 - 75 MHz Clock
from a Jittery or Intermittent 50 Hz to
30 MHz Clock Source
Highly Accurate PLL Multiplication Factor
– Maximum Error Less Than 1 PPM in High-
Resolution Mode
I²C / SPI™ Control Port
Configurable Auxiliary Output
Flexible Sourcing of Reference Clock
– External Oscillator or Clock Source
– Supports Inexpensive Local Crystal
Minimal Board Space Required
– No External Analog Loop-filter
Components
The CS2000-CP is an extremely versatile system
clocking device that utilizes a programmable phase
lock loop. The CS2000-CP is based on a hybrid ana-
log-digital PLL architecture comprised of a unique
combination of a Delta-Sigma Fractional-N Frequency
Synthesizer and a Digital PLL. This architecture allows
for both frequency synthesis/clock generation from a
stable reference clock as well as generation of a low-
jitter clock relative to an external noisy synchronization
clock. The design is also unique in that it can generate
low-jitter clocks relative to noisy external synchroniza-
tion clocks at frequencies as low as 50 Hz. The
CS2000-CP supports both I²C and SPI for full software
control.
The CS2000-CP is available in a 10-pin MSOP
package in Commercial (-10°C to +70°C), Automotive-
D (-40°C to +85°C), and Automotive-E (-40°C to
+105°C) grades. Customer development kits are also
available for device evaluation. Please see “Ordering
Information” on page 36 for complete details.
I²C/SPI
Software Control
I²C / SPI
3.3 V
Timing Reference
Frequency Reference
PLL Output
Lock Indicator
Auxiliary
Output
8 MHz to 75 MHz
Low-Jitter Timing
Reference
50 Hz to 30 MHz
Frequency
Reference
http://www.cirrus.com
Fractional-N
Frequency Synthesizer
Output to Input
Clock Ratio
N
Digital PLL & Fractional
N Logic
Output to Input
Clock Ratio
Copyright Cirrus Logic, Inc. 2009–2015
(All Rights Reserved)
6 to 75 MHz
PLL Output
SEPT '15
DS761F3




Cirrus Logic

CS2000-CP Datasheet Preview

CS2000-CP Datasheet

Fractional-N Clock Synthesizer & Clock Multiplier

No Preview Available !

CS2000-CP
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................................. 5
2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 6
3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 7
RECOMMENDED OPERATING CONDITIONS .................................................................................... 7
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 7
DC ELECTRICAL CHARACTERISTICS ................................................................................................ 7
AC ELECTRICAL CHARACTERISTICS ................................................................................................ 8
PLL PERFORMANCE PLOTS ............................................................................................................... 9
CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT ................................................. 10
CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT ............................................... 11
4. ARCHITECTURE OVERVIEW ............................................................................................................. 12
4.1 Delta-Sigma Fractional-N Frequency Synthesizer ......................................................................... 12
4.2 Hybrid Analog-Digital Phase Locked Loop .................................................................................... 12
4.2.1 Fractional-N Source Selection for the Frequency Synthesizer .............................................. 13
5. APPLICATIONS ................................................................................................................................... 14
5.1 Timing Reference Clock Input ........................................................................................................ 14
5.1.1 Internal Timing Reference Clock Divider ............................................................................... 14
5.1.2 Crystal Connections (XTI and XTO) ...................................................................................... 15
5.1.3 External Reference Clock (REF_CLK) .................................................................................. 15
5.2 Frequency Reference Clock Input, CLK_IN ................................................................................... 15
5.2.1 CLK_IN Skipping Mode ......................................................................................................... 15
5.2.2 Adjusting the Minimum Loop Bandwidth for CLK_IN ............................................................ 17
5.3 Output to Input Frequency Ratio Configuration ............................................................................. 19
5.3.1 User Defined Ratio (RUD), Frequency Synthesizer Mode .................................................... 19
5.3.2 User Defined Ratio (RUD), Hybrid PLL Mode ....................................................................... 19
5.3.3 Ratio Modifier (R-Mod) .......................................................................................................... 20
5.3.4 Effective Ratio (REFF) .......................................................................................................... 20
5.3.5 Fractional-N Source Selection ............................................................................................... 21
5.3.6 Ratio Configuration Summary ............................................................................................... 22
5.4 PLL Clock Output ........................................................................................................................... 23
5.5 Auxiliary Output .............................................................................................................................. 23
5.6 Clock Output Stability Considerations ............................................................................................ 24
5.6.1 Output Switching ................................................................................................................... 24
5.6.2 PLL Unlock Conditions .......................................................................................................... 24
5.7 Required Power Up Sequencing .................................................................................................... 24
6. SPI / I²C CONTROL PORT ................................................................................................................... 24
6.1 SPI Control ..................................................................................................................................... 25
6.2 I²C Control ...................................................................................................................................... 25
6.3 Memory Address Pointer ............................................................................................................... 27
6.3.1 Map Auto Increment .............................................................................................................. 27
7. REGISTER QUICK REFERENCE ........................................................................................................ 27
8. REGISTER DESCRIPTIONS ................................................................................................................ 28
8.1 Device I.D. and Revision (Address 01h) ........................................................................................ 28
8.1.1 Device Identification (Device[4:0]) - Read Only ..................................................................... 28
8.1.2 Device Revision (Revision[2:0]) - Read Only ........................................................................ 28
8.2 Device Control (Address 02h) ........................................................................................................ 28
8.2.1 Unlock Indicator (Unlock) - Read Only .................................................................................. 28
8.2.2 Auxiliary Output Disable (AuxOutDis) ................................................................................... 28
8.2.3 PLL Clock Output Disable (ClkOutDis) .................................................................................. 29
8.3 Device Configuration 1 (Address 03h) ........................................................................................... 29
8.3.1 R-Mod Selection (RModSel[2:0]) ........................................................................................... 29
8.3.2 Ratio Selection (RSel[1:0]) .................................................................................................... 29
2 DS761F3


Part Number CS2000-CP
Description Fractional-N Clock Synthesizer & Clock Multiplier
Maker Cirrus Logic
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