CAT5419 Datasheet | Catalyst Semiconductor

FEATURES - Two linear-taper digital potentiometers - 64 resistor taps per potentiometer - End to end resistance 2.5kΩ, 10kΩ, 50kΩ or 100kΩ - Potentiometer control and memory access via 2-wire Interface (I2C like) - Low wiper resistance, typically 80 - Four non-volatile wiper settings for each potentiometer - Recall of wiper settings at power up - 2.5 to 6.0 volt operation - Standby current less than 1µA - 1,000,000 nonvolatile WRITE cycles - 100 year nonvolatile memory data retention - 24-lead SOIC and 24-lead TSSOP - Write protection for data register DESCRIPTION The CAT5419 is two Digitally Programmable Potentiometers (DPP™) integrated with control logic and 16 bytes of NVRAM memory. A separate 6-bit control register (WCR) independently controls the wiper tap position for each DPP. Associated with each wiper control register are four 6bit non-volatile memory data registers (DR) used for storing up to four wiper settings. Writing to the wiper control register or any of the non-volatile data registers is via a 2-wire serial bus (I2C-like). On power-up, the contents of the first data register (DR0) for each of the two potentiometers is automatically loaded into its respective wiper control registers (WCR). ¯¯¯) pin protects against The Write Protection (WP inadvertent programming of the data register. The CAT5419 can be used as a potentiometer or as a two terminal, variable resistor. It is intended for circuit level or system level adjustments in a wide variety of applications. PIN CONFIGURATION SOIC (W) (top view) VCC RL0 RH0 RW0 A2 ¯¯¯ WP SDA A1 RL1 RH1 RW1 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 NC NC NC NC A0 NC A3 SCL NC NC NC NC SDA A1 RL1 RH1 RW1 GND NC NC NC NC SCL A3 For Ordering Information details, see page 15. TSSOP (Y) (top view) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 ¯¯¯ WP A2 RW0 RH0 RL0 VCC NC NC NC NC A0 NC RL0 RL1 A0 A1 A2 A3 CONTROL LOGIC NONVOLATILE DATA REGISTERS WP RW1 SCL SDA 2-WIRE BUS INTERFACE WIPER CONTROL REGISTERS FUNCTIONAL...