logo

NE33200 Datasheet, California Eastern

NE33200 fet equivalent, super low noise hj fet.

NE33200 Avg. rating / M : 1.0 rating-12

datasheet Download (Size : 87.71KB)

NE33200 Datasheet
NE33200
Avg. rating / M : 1.0 rating-12

datasheet Download (Size : 87.71KB)

NE33200 Datasheet

Features and benefits


* VERY LOW NOISE FIGURE: 0.75 dB typical at 12 GHz Optimum Noise Figure, NFOPT (dB) 4 3.5 NOISE FIGURE & ASSOCIATED GAIN vs. FREQUENCY VDS = 2 V, IDS = 10 mA 24 21 1.

Application

NEC's stringent quality assurance and test procedures assure the highest reliability and performance. Frequency, f (GH.

Description

The NE33200 is a Hetero-Junction FET chip that utilizes the junction between Si-doped AlGaAs and undoped InGaAs to create a two-dimensional electron gas layer with very high electron mobility. Its excellent low noise figure and high associated gain m.

Image gallery

NE33200 Page 1 NE33200 Page 2 NE33200 Page 3

TAGS

NE33200
SUPER
LOW
NOISE
FET
California Eastern

Manufacturer


California Eastern

Related datasheet

NE33284

NE33284A

NE33284A-SL

NE33284A-T1

NE33284A-T1A

NE334S01

NE334S01-T1

NE334S01-T1B

NE3002-VA10A

NE3004-VA10A

NE321000

NE3210S01

NE32400

Since 2006. D4U Semicon.   |   Contact Us   |   Privacy Policy   |   Purchase of parts