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CTS100ELT22TG - Dual CMOS/TTL to Differential PECL Translator

Download the CTS100ELT22TG datasheet PDF. This datasheet also covers the CTS100ELT22 variant, as both devices belong to the same dual cmos/ttl to differential pecl translator family and are provided as variant models within a single manufacturer datasheet.

General Description

The CTS100ELT22 is a dual CMOS/TTL to differential PECL translator.

Because PECL (Positive ECL) levels are used, only VCC and ground are required.

Key Features

  • 0.5ns Typical Propogation Delay.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CTS100ELT22-CTS.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number CTS100ELT22TG
Manufacturer CTS
File Size 212.42 KB
Description Dual CMOS/TTL to Differential PECL Translator
Datasheet download datasheet CTS100ELT22TG Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CTS100ELT22 Dual CMOS/TTL to Differential PECL Translator MSOP8, SOIC8 FEATURES  0.5ns Typical Propogation Delay  <100ps Typical Output to Output Skew  Flow Through Pinouts  Differential PECL Output  RoHS Compliant Pb Free Packages BLOCK DIAGRAM DESCRIPTION The CTS100ELT22 is a dual CMOS/TTL to differential PECL translator. Because PECL (Positive ECL) levels are used, only VCC and ground are required. The small outline packaging and the low skew, dual gate design of the CTS100ELT22 makes it ideal for applications that require the translation of a clock and a data signal. The CTS100ELT22 is a direct replacement for the ON Semi MC100ELT22, MC100LVELT22 and Micrel SY89322V.