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C8051 Datasheet Preview

C8051 Datasheet

Legacy-Speed 8-Bit Processor Core

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C8051
Legacy-Speed 8-Bit
Processor Core
General Description
The C8051 processor core is a single-chip, 8-bit
microcontroller that executes all ASM51
instructions and has the same instruction set and
timing of the 80C31. On-chip debugging is an
option.
The microcode-free design was developed for
reuse in ASICs and FPGAs. It is strictly
synchronous, with positive-edge clocking
(except for a flip-flop for internal reset and
two flip-flops for gated clocks in the PMU), no
internal tri-states and a synchronous reset.
Scan insertion is therefore straightforward.
Symbol
reset C8051
clk
p0i
p1i
ea p2i
p3i
ale
psen p0o
p1o
clkcpu
clkper
p2o
p3o
clkcpuo
clkpero
ramdatai
ramdatao
sfrdatai
sfrdatao
sfraddr
ramaddr
ramwe
ramoe
sfroe
sfrwe
romdatai
romaddr
romoe
Features
8-bit Control Unit
8-bit Arithmetic-Logic Unit with 8-bit
multiplication and division
Instruction decoder
Four 8-bit Input / Output ports
Two 16-bit Timer/Counters
Serial Peripheral Interface in full duplex mode
Synchronous mode, fixed baud rate
8-bit & 9-bit UART mode, variable baud rate
9-bit UART mode, fixed baud rate
Multiprocessor communication
Two Level Priority Interrupt System
5 Interrupt Sources
Internal Clock prescaler and Phase Generator
256 bytes of Read/Write Data Memory Space
64KB External Program Memory Space
64KB External Data Memory Space
Services up to 107 External Special Function
Registers
Power Management Unit supports stop and
idle modes
CAST, Inc.
August 2002
Page 1




CAST

C8051 Datasheet Preview

C8051 Datasheet

Legacy-Speed 8-Bit Processor Core

No Preview Available !

C8051 Core Datasheet
Pin Description
The C8051 contains only unidirectional pins. For proper communications via bi-directional Ports 0-3, it is
necessary to use in-circuit Open Drains.
Name
p0i
p0o
p1i
p1o
p2i
p2o
p3i
p3o
clk
reset
ale
Type
I
O
I
O
I
O
I
O
I
I
O
ea I
psen
O
romdatai O
romaddr O
romoe O
ramdatai I
ramdatao O
ramaddr O
ramwe O
ramoe O
sfrdatai
sfrdatao
sfraddr
sfrwe
sfroe
clkcpu
I
O
O
O
O
I
clkper I
clkcpuo O
clkpero O
Polarity/
Bus size
8
8
8
8
8
8
8
8
Rise
High
High
Low
Low
8
14
High
8
8
8
High
High
8
8
7
High
High
Rise
Rise
Rise
Rise
Description
Port 0: 8-bit bi-directional I/O port with separated inputs and outputs. Port 0 is
also the multiplexed low-order address and data bus during accesses to external
program and data memories.
Port 1: 8-bit bi-directional I/O port with separated inputs and outputs. Port 1 also
serves the special features.
Port 2: 8-bit bi-directional I/O port with separated inputs and outputs. Port 2 emits
the high-order address byte during fetches from external program memory that
use 16-bit addresses (MOVX @DPTR).
Port 3: 8-bit bi-directional I/O port with separated inputs and outputs. Port 3 also
serves special features.
Clock: A pulse for internal clock counters and all synchronous circuits.
Hardware reset input: Resets the device when this pin is held high for two clock
cycles while the oscillator is running.
Address Latch Enable: A pulse for latching the low byte of the Address during an
access to external memory. In normal operations, ‘ale’ is driven at a constant rate
of 1/6 the oscillator frequency.
External Access Enable: The ‘ea’ must be externally held low to enable the device
to fetch code from external program memory 0000H and 0FFFH. If ‘ea’ is held
high, the device executes from in-circuit program memory unless the Program
counter contains an address greater than 0FFFH.
Program Store Enable: The read strobe to external program memory. When the
C8051 is executing code from the external program memory, ‘psen’ is activated
each machine cycle; ‘psen’ is not activated during fetches from in-circuit program
memory.
Internal Program Memory interface:
Memory data bus
Memory address bus
Memory output enable
Internal Data Memory interface:
Memory data bus input
Memory data bus output
Memory address bus
Memory write enable
Memory output enable
External Special Function Registers interface:
SFR data bus input
SFR data bus output
SFR address bus
SFR write enable
SFR output enable
Engine clock A pulse for internal circuits that are stopped when the C8051 is in
IDLE or STOP mode
Peripheral clock A pulse for internal circuits that are stopped when the C8051 is in
STOP mode
Engine clock output The gated clkcpu clock. Clkcpuo stays low when the C8051
enters IDLE or STOP mode. The clkcpuo is dedicated to off-core connection to the
clkcpu input.
Peripheral clock output The gated clkper clock. Clkpero stays low when the C8051
enters into STOP mode. The clkpero is dedicated to off-core connection to the
clkper input.
CAST, Inc.
August 2002
Page 2


Part Number C8051
Description Legacy-Speed 8-Bit Processor Core
Maker CAST
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C8051 Datasheet PDF






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