SM55161A
Overview
- Organization: - DRAM: 262 144 by 16 Bits - SAM: 512 by 16 Bits
- Dual-Port Accessibility - Simultaneous and Asynchronous Access From the DRAM and SAM Ports
- Bidirectional Data-Transfer Function From the DRAM to the Serial-Data Register, and from Serial Data Register to DRAM
- (8 x 8) x 2 Block Write feature for fast area fill
- Write-Per-Bit Feature for Selective Write to Each RAM I/O; Two Write-Per-Bit Modes to Simplify System Design
- Byte-Write Control (CASL, CASU) Provides Flexibility
- Extended Data Output for Faster System Cycle Time
- Enhanced Page-Mode Operation for Faster Access
- CAS-Before-RAS (CBR) and Hidden-Refresh Modes
- Long Refresh Period: Every 8 ms (Maximum)
