SAMA5D21 Datasheet | Atmel

Features - ARM Cortex-A5 core ̶ ARMv7-A architecture ̶ ARM Trust Zone ̶ NEON™ Media Processing Engine ̶ Up to 500 MHz ̶ ETM/ETB 8 Kbytes - Memory Architecture ̶ Memory Management Unit ̶ 32-Kbyte L1 data cache, 32-Kbyte L1 instruction cache ̶ 128-Kbyte L2 cache configurable to be used as an internal SRAM ̶ One 128-Kbyte scrambled internal SRAM ̶ One 160-Kbyte internal ROM - 64-Kbyte scrambled and maskable ROM embedding Atmel boot loader/Atmel Secure boot loader - 96-Kbyte unscrambled, unmaskable ROM for NAND Flash BCH ECC table ̶ High-bandwidth scramblable 16-bit or 32-bit Double Data Rate (DDR) multiport dynamic RAM controller supporting up to 512 Mbyte 8-bank DDR2/DDR3 (DLL off only)/DDR3L (DLL off only)/LPDDR1/LPDDR2/LPDDR3, including “on-the-fly” encryption/decryption path ̶ 8-bit SLC/MLC NAND controller, with up to 32-bit Error Correcting Code (PMECC) Atmel-11267E-ATARM-SAMA5D2-Datasheet_25-Jul-16 - System running up to 166 MHz in typical conditions ̶ Reset controller, shutdown controller, periodic interval timer, independent watchdog timer and secure Real-Time Clock (RTC) with clock calibration ̶ One 600 to 1200 MHz PLL for the system and one 480 MHz PLL optimized for USB high speed ̶ Digital fractional PLL for audio (11.2896 MHz and 12.288 MHz) ̶ Internal low-power 12 MHz RC and 32 KHz typical RC ̶ Selectable 32.768-Hz low-power oscillator and 8 to 24 MHz oscillator ̶ 51 DMA Channels including two 16-channel 64-bit Central DMA Controllers ̶ 64-bit Advanced Interrupt Controller (AIC) ̶ 64-bit Secure Advanced Interrupt Controller (SAIC) ̶ Three programmable external clock signals - Low-Power Modes ̶ Ultra Low-power mode with fast wakeup capability ̶ Low-power Backup mode with 5-Kbyte SRAM and Sleep Walking™ features - Wakeup from up to nine wakeup pins, UART reception, analog parison - Fast wakeup capability - Extended Backup mode with DDR in Self-Refresh mode - Peripherals ̶ LCD TFT controller up to 1024x768, with four overlays, rotation, post-processing and...