Application/Master Core ̶ ARM Cortex-M4 running at up to 120 MHz(1) ̶ Memory Protection Unit (MPU) ̶ DSP Instruction ̶ Thumb®-2 instruction set ̶ Instruction and Data Cache Controller with 2 Kbytes Cache Memory ̶ Memories.
Up to 2 Mbytes of Embedded Flash for Program Code (I-Code bus) and Program Data (D-Code bus) with Built-in ECC (2-bit error detection and 1-bit correction per 128 bits).
Up to 256 Kbytes of Embedded SRAM (SRAM0) for Program Data (System bus).
8 Kbytes of R.
📁 Related Datasheet
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