* SDR Data sampling method
* CLK frequency up to 200MHz Data rate
  – up to 200MB/s
* 8-bits bus width supported
* Single ended signaling w.

CLK I Clock DAT0 I/O/PP Data DAT1 I/O/PP Data DAT2 I/O/PP Data DAT3 I/O/PP Data DAT4 I/O/PP Data DAT5 I/O/PP Data DAT6 I/O/PP Data DAT7 I/O/PP Data CMD I/O/PP/OD Command/Response RST_n I Hardware reset VCC S Supply v.

P3204HV

P3202CMA

P3202CMG

P3203AA

P3203AB

P3203AC

P3203ACMC

P3203CMG

P3203EVG

P3203UA

P3203UB

P3203UC

P3205

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