900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf




Analog Devices Semiconductor Electronic Components Datasheet

PKD01 Datasheet

Monolithic Peak Detector with Reset-and-Hold Mode

No Preview Available !

aheet4U.com wMitohnRoelistheitc-aPneda-kHoDPledKtDMe0co1tdoerFEATURES
SMonolithic Design for Reliability and Low Cost
taHigh Slew Rate: 0.5 V/s
aLow Droop Rate
.DTA = 25؇C: 0.1 mV/ms
TA = 125؇C: 10 mV/ms
wLow Zero-Scale Error: 4 mV
wDigitally Selected Hold and Reset Modes
w Reset to Positive or Negative Voltage Levels
Logic Signals TTL and CMOS Compatible
mUncommitted Comparator On-Chip
oAvailable in Die Form
t4U.cGENERAL DESCRIPTION
eThe PKD01 tracks an analog input signal until a maximum
eamplitude is reached. The maximum value is then retained as a
peak voltage on a hold capacitor. Being a monolithic circuit, the
hPKD01 offers significant performance and package density
advantages over hybrid modules and discrete designs without
Ssacrificing system versatility. The matching characteristics
attained in a monolithic circuit provide inherent advantages
tawhen charge injection and droop rate error reduction are
primary goals.
aInnovative design techniques maximize the advantages of mono-
lithic technology. Transconductance (gm) amplifiers were chosen
over conventional voltage amplifier circuit building blocks. The
.Dgm amplifiers simplify internal frequency compensation, minimize
acquisition time and maximize circuit accuracy. Their outputs
are easily switched by low glitch current steering circuits. The
wsteered outputs are clamped to reduce charge injection errors
upon entering the hold mode or exiting the reset mode. The inher-
wently low zero-scale error is further reduced by active Zener-Zap
mtrimming to optimize overall accuracy.
FUNCTIONAL BLOCK DIAGRAM
+IN –IN
OUTPUT V+
V–
LOGIC
GND
DET
–IN
+IN
–IN
+IN
RST
CMP
+
GATED
"gm"
AMP
A
+
GATED
"gm"
AMP
B
+
V–
OUTPUT
BUFFER
D1 C
+
PKD01
OUTPUT
RST
0
0
1
1
DET
0
1
1
0
OPERATIONAL MODE
PEAK DETECT
PEAK HOLD
RESET
INDETERMINATE
CH
SWITCHES SHOWN FOR:
RST = “0,” DET = “0”
The output buffer amplifier features an FET input stage to
reduce droop rate error during lengthy peak hold periods. A bias
current cancellation circuit minimizes droop error at high ambi-
ent temperatures.
Through the DET control pin, new peaks may either be detected
or ignored. Detected peaks are presented as positive output
levels. Positive or negative peaks may be detected without
additional active circuits, since Amplifier A can operate as an
inverting or noninverting gain stage.
An uncommitted comparator provides many application options.
Status indication and logic shaping/shifting are typical examples.
w ataSheet4U.coREV. A
.DInformation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
wuse, nor for any infringements of patents or other rights of third parties
wwhich may result from its use. No license is granted by implication or
wotherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001


Analog Devices Semiconductor Electronic Components Datasheet

PKD01 Datasheet

Monolithic Peak Detector with Reset-and-Hold Mode

No Preview Available !

PKD01–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ VS = ؎15 V, CH = 1000 pF, TA = 25؇C, unless otherwise noted.)
Parameter
Symbol Conditions
PKD01A/E
PKD01F
Min Typ Max Min Typ Max Unit
gm AMPLIFIERS A, B
Zero-Scale Error
VZS
24
Input Offset Voltage
VOS
23
Input Bias Current
IB
80 150
Input Offset Current
IOS
20 40
Voltage Gain
AV RL = 10 k, VO = ± 10 V
18 25
Open-Loop Bandwidth
BW AV = 1
0.4
Common-Mode Rejection Ratio CMRR –10 V VCM +10 V
80 90
Power Supply Rejection Ratio PSRR ± 9 V VS ≤ ± 18 V
Input Voltage Range1
VCM
86 96
± 10 ± 11
Slew Rate
SR
0.5
Feedthrough Error1
VIN = 20 V, DET = 1, RST = 0 66 80
Acquisition Time to
0.1% Accuracy1
tAQ 20 V Step, AVCL = +1
41 70
Acquisition Time to
0.01% Accuracy1
tAQ 20 V Step, AVCL = +1
45
3 7 mV
3 6 mV
80 250 nA
20 75 nA
10 25
V/mV
0.4 MHz
74 90
dB
76 96
dB
± 10 ± 11
V
0.5 V/µs
66 80
dB
41 70 µs
45 µs
COMPARATOR
Input Offset Voltage
Input Bias Current
Input Offset Current
Voltage Gain
Common-Mode Rejection Ratio
VOS
IB
IOS
AV
CMRR
Power Supply Rejection Ratio PSRR
Input Voltage Range1
VCM
Low Output Voltage
VOL
“OFF” Output Leakage Current IL
Output Short-Circuit Current ISC
Response Time2
tS
2 kPull-Up Resistor to 5 V
–10 V VCM +10 V
± 9 V VS ≤ ± 18 V
ISINK 5 mA, Logic GND = 0 V
VOUT = 5 V
VOUT = 5 V
5 mV Overdrive, 2 kPull-Up
Resistor to 5 V
0.5 1.5
700 1000
75 300
5 7.5
82 106
76 90
± 11.5 ± 12.5
–0.2 +0.15 +0.4
25 80
7 12 45
150
1 3 mV
700 1000 nA
75 300 nA
3.5 7.5
V/mV
82 106
dB
76 90
dB
± 11.5 ± 12.5
V
–0.2 +0.15 +0.4 V
25 80 µA
7 12 45 mA
150 ns
DIGITAL INPUTS – RST, DET2
Logic “1” Input Voltage
Logic “0” Input Voltage
Logic “1” Input Current
Logic “0” Input Current
VH
VL
IINH
IINL
VH = 3.5 V
VL = 0.4 V
2 2V
0.8 0.8 V
0.02 1
0.02 1 µA
1.6 10
1.6 10 µA
MISCELLANEOUS
Droop Rate3
Output Voltage Swing:
Amplifier C
Short-Circuit Current:
Amplifier C
Switch Aperture Time
Switch Switching Time
Slew Rate: Amplifier C
Power Supply Current
VDR TJ = 25°C
TA = 25°C
VOP DET = 1
RL = 2.5 k
ISC
tAP
ts
SR RL = 2.5 k
ISY No Load
0.01 0.07
0.02 0.15
± 11.5 ± 12.5
7 15 40
75
50
2.5
57
0.01 0.1 mV/ms
0.03 0.20 mV/ms
± 11 ± 12
V
7 15 40 mA
75 ns
50 ns
2.5 V/µs
6 9 mA
NOTES
1Guaranteed by design.
2DET = 1, RST = 0.
3Due to limited production test times, the droop current corresponds to junction temperature (TJ). The droop current vs. time (after power-on) curve clarified this point. Since
most devices (in use) are on for more than 1 second, ADI specifies droop rate for ambient temperature (TA) also. The warmed-up (TA) droop current specification is correlated
to the junction temperature (TJ) value. ADI has a droop current cancellation circuit that minimizes droop current at high temperature. Ambient (TA) temperature specifications
are not subject to production testing.
Specifications subject to change without notice.
–2– REV. A


Part Number PKD01
Description Monolithic Peak Detector with Reset-and-Hold Mode
Maker Analog Devices
PDF Download

PKD01 Datasheet PDF






Similar Datasheet

1 PKD01 Monolithic Peak Detector with Reset-and-Hold Mode
Analog Devices





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z



Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy