HMC698LP5E Datasheet | Analog Devices

Features Ultra Low SSB Phase Noise Floor: -153 d Bc/Hz @ 10 k Hz offset @ 100 MHz Reference Frequency. Programmable Divider (N= 12 - 259) Operating up to 7 GHz Open Collector Output Buffer Amplifiers for Interfacing w/ Op-Amp Based Loop Filter Reversible Polarity PFD w/ Lock Detect Output 32 Lead 5x5mm SMT Package: 25mm2 General Description The HMC698LP5(E) is a frequency synthesizer with a wideband reversible polarity digital PFD and lock detect output. The divider operates unconditionally from 80 - 7000 MHz with a continuous integer division ratio of 12 to 259. The HMC698LP5(E) high frequency operation along with ultra low phase noise floor make possible synthesizers with wide loop bandwidth and low N resulting in fast settling and very low phase noise. When used in conjunction with a differential loop filter, the HMC698LP5(E) can be used to phase lock a VCO to a reference oscillator. - INTEGER-n synthesizer - SMT 6-1 Electrical Specifications, TA = +25° C, Vcc = Vcc1 = Vcc2 = Vcc3 = Vcc_pd = 5V Parameter Maximum Ref. Input Frequency Minimum Ref. Input Frequency Reference Input Power Range Maximum VCO Input Frequency Minimum VCO Input Frequency VCO Input Power Range Conditions Sine or Square Wave Input [1] Square Wave Input [2] 100 MHz Frequency 100 MHz Input Frequency Min. Typ. Max. -5 +5 -10 +5 PFD Output Voltage PFD Gain Gain = Vpp / 2π Rad. SSB Phase Noise @ 10 k Hz Offset @ 100 MHz Square Wave Ref. Input Pin= 0 d Bm -153 Total Supply Current [1] Maximum frequencies may be limited by available counter division...