HMC6832 buffer equivalent, 2:8 differential fanout buffer.
Ultralow noise floor: −165.9 dBc/Hz or −165.2 dBc/Hz (LVPECL or LVDS) at 2000 MHz
Configurable to LVPECL or pseudo LVDS outputs 2.5 V or 3.3 V LVPECL operation (LVDS 2.5 .
SONET, Fibre Channel, GigE clock distribution ADC/DAC clock distribution Low skew and jitter clocks Wireless/wired commu.
The HMC6832 is an input selectable, 2:8 differential fanout buffer designed for low noise clock distribution. The IN_SEL control pin selects one of the two differential inputs. This input is then buffered to all eight differential outputs. The low ji.
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