Datasheet4U Logo Datasheet4U.com

ADSP-TS101S - TigerSHARC Embedded Processor

General Description

GENERAL DESCRIPTION 2 Dual Compute Blocks

.

.

.

.

.

.

.

.

.

Key Features

  • 300 MHz, 3.3 ns Instruction Cycle Rate 6M Bits of Internal.
  • On-Chip.
  • SRAM Memory 19 mm ؋ 19 mm (484-Ball) or 27 mm ؋ 27 mm (625-Ball) PBGA Package Dual Computation Blocks.
  • Each Containing an ALU, a Multiplier, a Shifter, and a Register File Dual Integer ALUs, Providing Data Addressing and Pointer Manipulation Integrated I/O Includes 14 Channel DMA Controller, External Port, Four Link Ports, SDRAM Controller, Programmable Flag Pins, Two Timers, and Timer Expired Pin for Syste.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
ADS-1011 2.5us Sampling A/D Converter DATEL
ADS-112 Low-Power Sampling A/D Converters DATEL
ADS-117 Low-Power Sampling A/D Converters Datel
ADS-118 Low-Power Sampling A/D Converters DATEL
ADS-118A Low-Power Sampling A/D Converters DATEL

Other Datasheets by Analog Devices

Part Number Description
ADSP-TS201S TigerSHARC-R Embedded Processor
ADSP-TS202S TigerSHARC Embedded Processor
ADSP-TS203S TigerSHARC Embedded Processor
ADSP-1010A 16 X 16-Bit CMOS Multiplier / Accumulator
ADSP-2100A DSP Microcomputers

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com a KEY FEATURES 300 MHz, 3.3 ns Instruction Cycle Rate 6M Bits of Internal—On-Chip—SRAM Memory 19 mm ؋ 19 mm (484-Ball) or 27 mm ؋ 27 mm (625-Ball) PBGA Package Dual Computation Blocks—Each Containing an ALU, a Multiplier, a Shifter, and a Register File Dual Integer ALUs, Providing Data Addressing and Pointer Manipulation Integrated I/O Includes 14 Channel DMA Controller, External Port, Four Link Ports, SDRAM Controller, Programmable Flag Pins, Two Timers, and Timer Expired Pin for System Integration 1149.