Dual enhanced SHARC+ high performance floating-point cores Up to 500 MHz per SHARC+ core Up to 5 Mb (640 kB) Level 1 (L1) SRAM memory per core with parity (optional abili.

SYSTEM CONTROL SECURITY AND PROTECTION SYSTEM PROTECTION (SPU) SYSTEM MEMORY PROTECTION UNIT (SMPU) FAULT MANAGEMENT Ar.

................................................. 3 Arm Cortex-A5 Processor ....................................... 5 SHARC Processor ................................................. 6 SHARC+ Core Architecture .................................... 8 .

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