Download the ADSP-CM419F datasheet PDF.
This datasheet also covers the ADSP-CM411F variant, as both devices belong to the same mixed-signal dual-core control processor family and are provided as variant models within a single manufacturer datasheet.
Description
3 Analog Front End 4 Dual-Core System Architecture 10 EmbeddedICE 13 Processor Infrastructure 13 Memory Architecture 17 System Acceleration 19 Security
Features
- Up to 240 MHz ARM Cortex-M4 with floating-point unit with up to 160K Byte zero-wait-state ECC SRAM
Safety based dual independent- core concept Up to 1M Byte high performance ECC FLASH that can execute
instructions at near SRAM speed Highest precision, low latency 31-channel analog front end 100 MHz ARM Cortex-M0 supervisor core with 32K Byte zero
wait state ECC SRAM Single 3.3 V power supply Static memory controller (SMC) with asynchronous memory
interface that supports 8-bit and 16-bit memories.
ADSP-CM419F Datasheet
